Hi,

I have a design based on the HMC699 PLL and HMC584 VCO with a CW output of 13.6GHz. Everything works just fine and the phase noise measurements match the simulation very good. However I have several high spurs close to the F0. The ref oscillator…

Hi all,

We have built our prototype following the indications form the datasheet and the circuit example but it does not work, there is no Loop Lock and the HMC699 gets very very hot. The system must lock to 5920MHz, we asked for the programming registers…

Hi All,

I am involved in a new design based on HMC699, I need to generate a 5920MHz signal with a reference input of 20MHz.

I have simulated the system using ADISim PLL and the chip programming assitant Gives me 37 (with other names) for the programming…

Hi There,

I have inherited a design which uses a HMC699 Integer N PLL chip to lock an external VCO @ 4.6GHz using an external 10MHz reference clock.

http://www.synergymwave.com/products/vco/datasheet/DCYS250510-5.pdf

The Up/Down PFD outputs are…

I need to design a 12-13 GHz low-noise frequency synthesizer based on the HMC699# PLL# and the HMC583# VCO#.

Is it possible to have their models to simulate this system with Hittite's design tool v1.15 that I have downloaded from your site?

By the…

Hi Huangzeyan,

Thank you very much for your useful answer.

I have still a couple of questions:

1) Which is the best opamp you may suggest to keep the phase noise as low as possible?

2) I am missing the reason why the phase detector gain is set to…

Hi all,

I'm trying to recreate the PLL design that is in the HMC699 datasheet on page 11 (https://www.analog.com/media/en/technical-documentation/data-sheets/hmc699.pdf).

First I would like to simulate it exactly in ADI SIM PLL.

So far this is the…