• HMC6832 & HMC987

    On the HMC6832, 

    1. are there any phase noise plots on the part, the data sheet does not show any information on close in noise at higher frequency’s, my operating range would be from ~500 to 3200MHz
    2. The data sheet in figure 12 shows relative output…
  • HMC6832 SYSREF distribution

    Hello, I would like to use HMC6832 for CLK distribution to ADCs (AD6676). I consider using another HMC6832 for SYSREF distribution as well but I am not sure about HMC minimum operation frequency - 10MHz... because SYSREF is one or several pulses signal…

  • HMC6832 output drive level

    The HMC6832 data sheet states that its differential output voltage swing is 721mVpp typ when used in 3V3 LVPECL mode. To check: presumably, this is the swing of each output in the differential pair, so that the full differential output swing is 1.4Vpp…

  • HMC6832 Demo Board Gerber

    Dear All:

    I Need EVAL-HMC6832 demo board gerber file to design my PCBA ,can you provide file to me refer? thanks

    Best Regards,

    Jack

  • Can I use HMC6832 for LVDS data clock fanout?

    Hi!
    Early we used HMC6832 for continuous clock fanout.
    But now we also want to use HMC6832 for LVDS data clock fanout for protocol like spi but using LVDS signals. LVDS clock input can interrupt sometimes but then appears again.
    I want to use next schematic…

  • RE: HMC833 to HMC987 interface

    The interface should look like...

    The max input reference for the HMC833 is 350 MHz.  50 MHz will work fine.

    The HMC987 provides 8 LVPECL outputs and a single CML output.   If the LVDS receiver can handle the 800mVpp HMC987 output levels you can connect…

  • TAGS LIST: Clock and Timing

    LTC6953
    LTC6955
    LTC6957-1
    HMC6832
    HMC7043
    LTC6950
    LTC6954
    HMC987
    AD9576
    AD9508
    HMC1035
    HMC988
    HMC1033
    HMC1034
    HMC1032
    HMC1031
    ADN4670
    ADCLK944
    ADCLK950
    ADCLK948
    ADCLK846
    ADCLK954
    ADCLK946
    ADCLK854
    AD…