• Can I always pull CSn low in SPI bus hooked up with only two device?

    Dear Sir,

    We only have two devices hooked up to SPI bus. Among them, ADuC7124 is slave and one CPLD is master. The ADu7124’s SPI bus
    mode is chosen as slave, phase mode:0, polarity: 0.
    Each data transfer between them is 16 bits. We have to  pull CSn high…

  • RE: Problem using additional program memory (Aduc 7026)

    You can use ADuC7124/26 - 128kByte FLASH & 32kByte SRAM

    The answer to the other questions is negative - you may need your own downloader for external Memory or via JTAG-Tools supporting this, i.e. KEIL µVision or IAR EW.

  • RE: SPI master speed limit

    With the ADuC702x we have seen problems on the MISO with higher speeds. The newer parts in the family, like ADuC7023, ADuC7121, ADuC7122, ADuC7124 and ADuC7126 have been improved and can run up to half the core clock, which means approximate 20MHz @ CD…

  • PWM on ADuC7060/61, how do I set the duty cycle of a PWM output?

    PWM on ADuC7060/61, how do I set the duty cycle of a PWM output? Source code would be nice.

    Since the same PWM design is on ADuC7060/61/ADuC7023/ADuC7121/ADuC7122/ADuC7124/26 parts, this question is also applicable to all of these.

  • RE: Can I use SPI ADuC706x for daisy chaining of multiple MCUs?

    1.) Larger and newer parts are ADuC7124 and ADuC7126 with this features including a HW UART, if a SW UART is not sufficient for your application.

    2.) yes it it possible to reprogram parts of the Flash from a running program, so called IAP (In Application…

  • RE: If using an ADI micorcontroller in a LFCSP package, how do I connect the exposed paddle on the underside of the package on my PCB?

    On the following parts, the exposed paddle is used for mechanical stability and should be connected to a large pad on your PCB but, this pad should not be connected to ground or any other track:

    ADuC7019, ADuC7020, ADuC7021, ADuC7022, ADuC7023, ADuC7024…

  • RE: ADuC7126 Pin P4.5 behavior when JTAG is connected

    Yes I did mean the aduc7124.
    If you look at the entire pinout of aduc7124 you will see that P0.1, 0.2 and 0.3 are actually missing.

    They are actually shared with the JTAG pins, but are not documented like that because customers attempted to use them as…

  • RE: ADuC7020: What is the minimum width of an external Reset Pulse?

    Because the ADuC7019/20/21/22/24/25/26/27/28/29 and ADuC7128/7129 parts have a Glitch immunity filter on their reset input circuitry, the minimum pulse width of an external reset signal should be 120uS to safely reset the part.

    Note, the ADuC7023/ADuC7060…

  • RE: Re: JTAG can not find ARM CPU ID

    If you don’t already have the CD, it can be downloaded from here.


    You will find the ARMWSD then in the following directory once installed.



  • RE: Remote FW download for the ADuC7026

    Hi David

    I would like to add at this stage that on our ARM7 based parts the chip condition after POR, pin, watchdog and software resets is the same.  You would not be able to tell which reset occured except for the following:

    The RSTSTA register flags…