• Input Source Color Space of ADV7611


    I am using ADV7611 HDMI receiver in our custom board , in that we are dynamically changing input source RGB or YCbCr color space and convert to output YCbCr format.

    Any ADV7611 register set is available to check the input source is RBG or YCbCr…

  • FPGA video processing with ADV7611

    Hi ADI,

       These is a video processing project I run like this : PC------(hdmi)-------> ADV7611-------(RGB24 SDR)--------> FPGA. The captured video stream is processed in FPGA.

    In FPGA, some processings must be processed in the clock domain of ADV7611…

  • ADV7611, ADV7612 scripts for 576i to HDMI out

    ADV7611, ADV7612 scripts for 576i to HDMI out by vito


    Attached script that takes in 576i (625i) HDMI in and gives output through encoder.

    This can be run in XRC. To be used with following boards





  • About register 68 6F of ADV7611

    Let me ask a question about register 68(HDMI Map) 6F of ADV7611.


    Your ADV7611 Recommended Settings document(Rev1.5) on the following site says that register 68 6F needs to be set to 0x08.

    Meanwhile, your script file(ADV7611-VER.3.0c.txt) says that register…

  • ADV7611 LLC Amplitude


    We are performing a board bring up on a new design using the ADV7611.  With this part we are receiving HDMI video and outputting 24-bit RGB from the CMOS.  The HDMI input is detecting correctly, but as we were checking the outputs we noticed…

  • ADV7611 Initialization

    We are trying to configure the ADV7611 on an Avnet AES-FMC-HDMI-CAM-G FMC. Apparently this board is a derivative of the earlier IMAGEON FMC.

    The FMC is installed on a Xilinx KCU105. We had to modify the board to use 3.3V rather than VADJ for the I2C switch…

  • ADV7611 mtbf value

    What is the FIT and MTBF value of ADV7611WBSWZ?

  • ADV7611 SDR 444 YCbCr out


    I think ADV7611 supports SDR 444 YCbCr out with following setting

    IO Address 0x03 OP_FORMAT_SEL ; 0x40

    IO Address 0x02[1] RGB_OUT=0(default)

    but this is not listed on PIXEL OUTPUT FORMATS in APPENDIX C, UG-180. ADV7611 Reference Manual (Rev. D) (analog…

  • ADV7611 YCbCr 4:2:2 SDR issue

    I am trying to configure ADV7611 to output 1280x1024 video in 16-bit SDR ITU-R BT.656 4:2:2 Mode 0.

    In free-run mode with blue background I get "0xFF00, 0x0000, 0xFF00, 0x0000..." pixel data, but it is 1280 LLC-period wide DE window between HSyncs…


    When i connect a DVI generator device to our system based on ADV7611, i read the information "FIFO is about to overflow", with the video FIFO locked.

    What is the meaning of this readback? How can i have more information about TMDS sampling …