• ADV7403 STANAG Colour Issue.

    Hi,

    I have the following requirements for ADV7403:

    I/P Video - STANAG 3350 with Sync On Green as Input to the Chip.

    1)720x576i @ 50/25Hz(Class B)video resolution, Interlaced video input,RGB(STANAG Class B)
    2)720x480i @ 60/30Hz(Class C)video resolution…

  • ADV7403 : PAL Video Horizontal Shaking Issue

    Hello,

    I am using ADV7403 for decoding CVBS Input ( (BT.656 format ). I am facing an issue with PAL Video output from the Chip.

    When PAL ( 720/576i) video is given to the chip, I am observing horizontal shaking, the video clip for the same is attached…

  • Hsync problem with ADV7403

    I have problem with Hsync.

    I program ADV7403:

        prim_mode 0x05 0x00

        vid_std 0x06 0x0B

        VCO Range[1:0] = 10

        PLL_QPUMP[2:0] = 010

    On a oscilloscope I saw, that Hsync frequency is 15625Hz and calculated Pll_div_ratio from equation  Fpixelclock / Fhsync…

  • ADV7403 Register Programming sequence Failure

    Dear Analog Devices Experts,

    I am configuring ADV7403 by writing data into corresponding registers as below.

    I understood from below data, 1st byte is slave address, 2nd byte is register address and 3rd byte is register data.
     
    As per this convention
  • ADV7403 S/W Download from ftp.analog.com

    Hi. 

    I've bought ADV7403 eval kit and received a paper in it regarding SW download via ftp. 

    But Your fpt.analog.com still have some problem, I don't get SW. 

    Simple solution:

    Please send the SW through E-mail. 

    Thank you in advance

  • RE: ADV7403 ADV7842 and ADV7850 chips

    Audio CODECs can be found here

    https://www.analog.com/en/parametricsearch/11357#/

    CODECs come with output DACs but you don't have to connect or use them them.  The key you are looking for is I2S bus, 2 input channels (ADCs) and 192k sampling rate.

  • RE: ADV7403 register configuration for STANAG 3350 CLASS B/C Video Signals

    Hi,

     If it is your own system could you make sure that there are no strong pull-up on the line or that the backend processor is not somehow preventing the interrupt pin driving low.

     If there is no crystal input connected, then the INTRQ pin remaining high…

  • ADV7403 Register Values for RGB Input and YUV 16bit 4:2:2 output

    Hi,

    I have a following script for a RGB input and YUV 422 output. 

    Reg Address Reg Data
    0x52 0x00
    0x53 0x00
    0x54 0x07
    0x55 0x0C
    0x56 0x94
    0x57 0x89
    0x58 0x48
    0x59 0x08
    0x5A 0x00
    0x5B 0x68
    0x5C 0x81
    0x5D 0x00
    0x5E 0x19
    0x…
  • RE: ADV7403 I2C read issue

    Dear Analog Device Experts

    I am Also facing same issue

    (i.e) WRITE TRANSATION is acknowledged by  the ADV7403 -- Working

            READ TRANSACTION is Not acknowledged by ADV7403 --Not Working

    After the Slave address 0x42 send by host , ADV7403 is pulling the…

  • ADV7403 support ST3350-A (875 line)

    Hi,

    We're using ADV7403 to AD convert ST3350-A video and send to FPGA. It's found that the automatic analog front end clamping always influence video brightness. We have tried use GR (1024x768) or CP (1080i) mode with proper PLL_DIV and FR_LL settings…