Input D is shown as schmidt in fig 2. I have slow input rise time input signal and ouput freq is not same as input.
What is the max rise time allowed on this input?
Please see customer circuit attached:
SP_3_3V is UP before 3.3VA.
During this time NW_ISO_56N_PS1_OFFLINE_FPGA (pin 6) is driven High (which in turn switches OFF main power supply controlled through NW_ISO_56N_PS1_OFFLINE_FPGA signal) .
ADI官方参考设计中DAC部分隔离芯片ADUM1401CRWZ是采用AD5422的DVCC引脚供电的，AD5422该引脚功率好像只有1mA的驱动 能力，远小于ADUM1401CRWZ的功耗，请问第一：你们的板子是否经过验证；第二：SPI总线的频率是多少；第三：ADUM1401CRWZ与 AD5422的功率匹配关系。
is it possible to use the ADUM 1401 as I²C isolator?
I thought about connecting pins 5 and 6 as well as 11 and 12 to realize the full duples SDA signal and achieve the same behavior as the ADUM 1251.
We’ve been doing some tests on above, and get considerable oscillation on output when i/p risetime is 100us or so. Please see attached screenshot: yellow trace is i/p signal, 4.9v p-p, risetime of 100us (ignore Y axis scale for signal – x10 probe attached…
We are concerned about an interval of bus contention during power-up between an ADUM1401 and a DSP processor. During power-up, the Side 1 power supply may lag behind Side 2. Therefore, the ADUM1401 outputs will be driven high. At the same time, the DSP…
Can anyone clarify what ADuM1401 side 1 drive value is? The data sheet tells only Absolute Maximum Ratings:
Average Output Current per Pin -18mA to + 18 mA
There are two ways to read this:
average/pin (3 outputs on this side) is max. 18 mA, total 54…