Please see customer circuit attached:
SP_3_3V is UP before 3.3VA.
During this time NW_ISO_56N_PS1_OFFLINE_FPGA (pin 6) is driven High (which in turn switches OFF main power supply controlled through NW_ISO_56N_PS1_OFFLINE_FPGA signal) .
Hi I would like create a bus SPI with two ADUM1401 and my master device.
I use like a MISO line VOD output of each ADUM1401.
|------(spi bus line MOSI)-------------master device
The PLC_DEMO_SYSTEM had been thoroughly tested including the isolated analog output channels with ADUM1401 and AD5422. The ADUM1401 is not designed to run at its highest data rate on the PLC_DEMO_SYSTEM. The working data rate might be less than 1MHz.…
I want to use ADuM1401 to isolate MCU and ADC.
The supply current of ADuM1401 is 31mA per channel when the frequency is 90Mbps, does it means the input signal current should be 31mA? As SPI driving current is several mA, how can I connect these…
We’ve been doing some tests on above, and get considerable oscillation on output when i/p risetime is 100us or so. Please see attached screenshot: yellow trace is i/p signal, 4.9v p-p, risetime of 100us (ignore Y axis scale for signal – x10 probe attached…
Input D is shown as schmidt in fig 2. I have slow input rise time input signal and ouput freq is not same as input.
What is the max rise time allowed on this input?
We are concerned about an interval of bus contention during power-up between an ADUM1401 and a DSP processor. During power-up, the Side 1 power supply may lag behind Side 2. Therefore, the ADUM1401 outputs will be driven high. At the same time, the DSP…
About ADuM1401 usage around VDD1 and VDD2.
One customer's application has two modes, normal and backup mode.
In normal mode, ADuM1401 both VDD1 and VDD2 are supplied 5V and 3V. There are no problem.
But when application go to backup mode…
北京 昌平区 医疗器械 关注AD5933 ADuM1401