• Problem setting up ADuC7129 UART for 3 MHz and 6 MHz

    Hi,

    I am having problems setting up the ADuC7129 UART interface for 3 MHz and 6 MHz. 

    CD DL M N Rate COM0DIV0 COM0DIV1 COM0DIV2 Notes
    0 1 0 892 2997668
  • RE: DDS

    ADuC7129 still needs a crystal or external clock, no?

  • ADuC7128/29 UARTs ?

    What are the right PINs for the two UARTs on the ADuC7128 and AduC7129 ?

    This is not absolute clear or easy to understand in the datasheet.

  • hardware question: is it possible to flash a memory without a debugger ? if so how?

    Hello.

    I have an ADuC7023. Is it possible to download the program to the uC not "through" debugger ??

    I checked the compatibility of ULINK 2 from KEIL, and as can be seen below ADuC7023 is not on that list. That is why I was wondering if…

  • RE: Writing COMxIEN Asserts TX Buffer Empty Interrupt?

    Paul,

    I would ideally like to have found “the standard” which defines exactly what should happen here, and find a “This is implementation dependent” statement regarding the THRE interrupt.

    I didn’t find that, only the statement “Transmitter Holding…

  • RE: ADuC7xxx How to transfer 16-bit units over SPI ?

    There are two possible solutions if in the system a delay of the FIQ can be accepted.

    1.) implementation of the continuous 2 byte transfer to be handled in a FIQ exception handler

    2.) disable the FIQ source (clear related bit in FIQCLR) during the transfer…

  • TAGS LIST: Processors & DSP

    ADUC812
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    ADUC824
    ADUC831
    ADUC832
    ADUC834
    ADUC836
    ADUC841
    ADUC842
    ADUC843
    ADUC845
    ADUC847
    ADUC848
    ADUC7019
    ADUC7020
    ADUC7021
    ADUC7022
    ADUC7023
    ADUC7024
    ADUC7025
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  • ADuC7XXX系列常见问题解答

    问题:ADUC7XXX系列的开发方法和开发工具是怎样的?

    答案:ADuC7XXX的开发方法是非常简便的。ADUC7XXX系列提供了三种评估板套件,以帮助用户熟悉ADuC7XXX的开发方法和开发环境。以ADUC7020和ADUC7026为例,一种是EVAL-ADuC7020MKZ,这是一种迷你套件,它包括一块迷你评估板,电源线和串行下载线;另一种是EVAL-ADUC7026QSZ,它包括一块评估板,9V电源,串行下载线,和相应的软件光盘;还有一种是EVAL-ADUC7026QSPZ,它与前一种的区别是包括了一个硬件仿真器…

  • Changing ADuC712x Core Clock Source with JTAG

    I see in a previous topic (http://ez.analog.com/message/11288#11288) that if the power management modes are enabled while using JTAG, the part must be mass erased.  This would seem to prevent using any core clock souce other than the internal oscillator…