• ADuC7129 : absolute maximum rating

    I have a question about the absolute maximum rating of ADuC7129.

    In data sheet P15 table 9 of this IC, the following maximum rating is written.

    " Digital Input Voltage to IOGND : −0.3 V to IOVDD + 0.3 V "

    However, other ADuC7xxx are written…

  • Sample Keil RTX Project with ADuC712x?

    Is there a sample project using Keil's RTX RTOS with the ADuC712x? The startup folder in the Keil installation folder includes an RTX configuration file for the ADuC702x, but I've already found that the names of some of the timer registers are different…

  • Sample/Example Code for I2C Download Protocol

    I am starting to implement the I2C Download Protocol [described in AN-806] for the ADuC7020 using a bigger microcontroller - ADuC7128. The Boot Mode(BM) pin and the reset are controlled by the 7128 to put the ADuC7020i into Boot Mode.

    I am wondering…

  • RE: ADuC7020: What is the minimum width of an external Reset Pulse?

    Because the ADuC7019/20/21/22/24/25/26/27/28/29 and ADuC7128/7129 parts have a Glitch immunity filter on their reset input circuitry, the minimum pulse width of an external reset signal should be 120uS to safely reset the part.

    Note, the ADuC7023/ADuC7060…

  • RE: Bad JTAG communication with ADuC7026

    Thanks for the help MMA,

    I tried to do a mass erase using the ARMWSD method, and tried to do it on the ADuC7128, and was able to successfully clean it. Then I did it on the ADuC7026, I received the following messages:

    My board doesn't actually have…

  • hardware question: is it possible to flash a memory without a debugger ? if so how?


    I have an ADuC7023. Is it possible to download the program to the uC not "through" debugger ??

    I checked the compatibility of ULINK 2 from KEIL, and as can be seen below ADuC7023 is not on that list. That is why I was wondering if…

  • RE: DDS

    It does not.  From page 49 of the datasheet:

    "The ADuC7128/ADuC7129 integrate a 32.768 kHz oscillator, a clock divider, and a PLL. The PLL locks onto a multiple (1275) of the internal oscillator to provide a stable 41.78 MHz clock for the system…

  • Changing ADuC712x Core Clock Source with JTAG

    I see in a previous topic (http://ez.analog.com/message/11288#11288) that if the power management modes are enabled while using JTAG, the part must be mass erased.  This would seem to prevent using any core clock souce other than the internal oscillator…

  • ARMWSD.exe for Windows PE


    Our device contains a module with an ADuC7128.  We use ARMWSD.exe v1.11 with command line arguments to update its software from within our Windows Embedded Standard 7 application and it works great.

    However, all the rest of our system's software…