• RE: SHARC core 2 stuck

    Hi Parikshit,

    Thanks for your information.

    These days, I ported you example into my sc589-ezkit board, it works well with the three-core communication following your comments.

    1. For ADSP-SC589: I think all of your options are correctly in using the MCAPI…
  • RE: USB hub for SC587

    Hi,

    We understand that you have already contacted our private support.Please continue the discussion there.We are posting the response here for others to benefit.

    USB HUB support is already available for SC587. You should be able to rebuild the existing…

  • Bounary Scan with ADSP-SC58x and ADSP-21584

    1. #boundary scan jtag_scan_failed

    Anyone having luck getting the ADSP-SC58x or ADSP-2158x series processors to work in boundary scan? JTAG Technologies "JTAG Live" device seems to read SC587 and 21584 chip ID's OK, but cannot read from boundary…

  • What is the length matching requirement for Link port?

    Hello, 

    Please anyone let us know that, what is the length matching requirement for Link port in ADSP-SC587 device? 

    Thanks and Regards

    Tarang Jindal

  • ADSP SC587 VDD_RTC current consumption

    Can anyone tell me how much current would the ADSP SC587 RTC section will consume from VDD_RTC rail? This is just to estimate the coin cell life time.

  • can we use 33E, 1% resistor to gnd for DMCx_RZQ pin of ADSp-SC587.

    Hello, 

    ADSP-SC587 datasheet suggest to use 34E resistor to gnd for DMCx_RZQ pin. 

    can we use 33E, 1% resistor instead of 34E resistor? 

    Please confirm. 

    Thanks and Regards

    Tarang Jindal

  • RE: ADSP-SC587 adi_rom_boot() for Second Stage Load

    Hello,

    As this query is closed in the private support, post the final resolution for others to get benefit.

    Seems that you call the adi_rom_boot function from SHARC core 2. In that case, as mentioned in EE-384, "If the ROM API is invoked from the secondary…

  • RE: SC-58x dynamically loading SHARC from ARM

    Hi,

    From the "SHARC+ Dual Core DSP with ARM Cortex-A5 ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587" document I can read the "mappings" for SHARC(s) L1 caches (table 6).

    As mentioned above we should be able to place SHARC…