• Regarding difference between BF609 and BF608.

    Hello,

    According to datasheet, a difference between BF609 and BF608 is PVP's performance. BF609 can do up to HD while BF608 can do up to VGA.

    What makes the two PVP's performance differenent each other?  Is BF608 PVP's clock rate slower than…

  • What is the difference between the PVP of the BF608 and BF609?

    Presently only the BF609 is being sampled. As characterization of the BF60x family continues updates will be made to this FAQ with the final specification differences between the BF608 and BF609. Characterization will be complete by release to production…

  • How many instances does UART have in ADSP-SC59x/ADSP-2159x processor?

    How many instances does UART have in ADSP-SC59x/ADSP-2159x processor?
  • How FFT accelerator (FFTA) on ADSP-SC58x/ADSP-2158x is different as compared to ADSP-214xx processors / What are the major features of FFTA on ADSP-SC58x/ADSP-2158x ?

    FFT Accelerator on ADSP-SC58x/ADSP-2158x is a completely new design as compared to the FFT accelerator on ADSP-214xx processors. The major differences/features of the FFT accelerator on ADSPSC58x/ADSP-2158x are:

    • Unlike in ADSP-214xx, the…
  • Porting software  from ADSP-21489 to ADSP-21573 and ADSP-SC573 

    Customer ask some questions.

    Right now we have  plenty of software for ADSP-21489, but it’s quite hard to port it to ADSP-SC573 family. Code itself

    is 99% C and C++.

     

    Does family ADSP-SC573 have interface with external static memory like AMI for ADSP…

  • prototyping the a ADSP-TS203S design with a ADSP-TS201s or a ADSP-TS202S

    We're currently laying out a prototype PCB to take an ADSP-TS203 TigerSHARC
    Processor (i.e. with only a 32 bit cluster bus and 2 link ports). Could we fit
    an ADSP-TS201/2 to this board if we constrict external bus access to 32 bits
  • RE: How many TRU Interrupts are there for each core in ADSP-SC59x/ADSP-2159x processor ?

    For the ADSP-SC59x/ADSP-2159x set of processors, there are four TRU interrupts from each core.

    TRU Interrupts 0-3 are dedicated to ARM core and TRU Interrupts 4-11 are dedicated to SHARC cores.

  • Does General Purpose Counter in ADSP-SC59x/ADSP-2159x processors detect overflow or underflow in the counter value?

    Does General Purpose Counter in ADSP-SC59x/ADSP-2159x processors detect overflow or underflow in the counter value? 

  • How DMC/DDR controller in ADSP-SC58x/ADSP-2158x different than DDR2 controller on ADSP-2146x ?

    ADSP-2146x

    ADSP-SC58x/ADSP-2158x

    Supports only DDR2 memory devices Supports DDR3, DDR2, and LPDDR memory devices
    Supports maximum clock/data rate of 225/450 MHz Supports maximum…
  • ADSP-SC5xx/ADSP-215xx

    EngineerZone technical forum that provides customer support for Analog Devices ADSP-SC5xx/ADSP-215xx products.