• TAGS LIST: Blackfin Processors

  • Some problem about Linking DSP Library

    Hello ,


    I'm working on BF549 ,  after compile and link , I read the file(.map.xml) in the Debug fold,   I find many libdsp532.dlb  in L1_CODE memory, it takes so many space that My program code have to move to sdram.


    I read the PDF (VisualDSP…

  • RE: AD9364 Init Config Issue


    I'm confused -- I thought you said you didn't have an FPGA? If you do, it changes the answers we give.

    What does your system look like?

    AD9361 -> Data path -> FPGA -> BF538

    AD9361 -> SPI -> BF538


  • RE: Question about silicon revision

    Hi Lloyd,

    I have tryed this, but I am using SPI boot method. Apparently the lower silicon revisions doesn´t support boot via SPI.

    Sorry I have forgot to mention that.

    The compilation will fail as follow:

    [Warning ld0079]: Ignore programmable flag…


    Hello guys,

    I am working on configuring a slave device with ADSP-BF538F and I am able to generate SPI clock and Slave select. The isssue is that I find no signal getting generated on the MOSI pin. I checked the return value of submitbuffer function which…

  • RE: How many admp441 mics can I attach to BF592 via sport?

    Hi MartyD,

    The ADSP-BF592 Blackfin DSP has two SPORTs with 2 data lines per SPORT, so there are a total of 4 data lines. In I2S mode, each of these data lines can support 2-channel input, so you could get up to 8 channels of data directly from the A…

  • Resampling on BF538 Eval board

    I am attempting to upsample data sampled at 24kHz to 44Khz. I intend to upsample by 11 and downsample by 7. When I try to do this, I can get what I want but the output sounds extremely noisy. There seems to be a background hissing sound. The anti-aliasing…

  • 3 Phase PDM generators

    One of my customers has used in the past the ADSP BF538 that has a 3 phase PDM generator.

    In an effort to reduce cost for a lighter version, they are looking at the BF512 and need to generate two modulated PDM singanls.

    He is thinking to use the timer…

  • RE: Pin Muxing in CCES 1.1.0 for ADSP-BF538F

    Hi Anand,

    The peripherals mapped to Port F (SPI0, PPI and Timers) don't use the Pin Muxing Add-in because Port F doesn't have a Function Enable register (FER).  The peripherals on Port F are enabled directly from the peripheral control/config…

  • RE: 4 x ADAU1761 in TDM8

    We use a custom designed board with a Blackfin BF538. The BF538 has 4 SPORT ports but 3 of hem are already in use by other codecs and a FPGA, the 4th will be used to connect 8 ADAU1761's, 4 on the primary channel and 4 on the secundary channel. So the…