• BF527 PLL setting

    Could you explain me which way of PLL setting for BF527 is correct?

    There is information:

    "Note that the divisor ratio must be chosen to limit the system

    clock frequency to its maximum of fSCLK. The SSEL value can be

    dynamically changed without…

  • RE: BF527 power up sequence

    Hi Eamonn,

    Although Blackfin processors have no power-up sequencing requirements, a silicon anomaly on existing ADSP-BF527 silicon revisions (0.0, 0.1 and 0.2) may lead to PLL issues when VDDINT is powered before VDDEXT. This very same issue is discussed…

  • BF523 HOST Port interface(HOSTDP)

    Hi,


    I have a issue with regards BF523 HOST Port interface(HOSTDP).

    We are trying data transfer from host Device and blackfin and we find that the
    Host access and the Blackfin response is not matching with the working .
    This is same with both Acknowledge…

  • RE: What is the maximum DDR size that BF54x can support?

    Hi

    What is the maxium Size support for BF523/5/7 and what is the maximium for BF522/4/6

    Data sheet and manual is a bit confusing .

    Thanking you

  • RE: Can BF52x processors be booted from NAND flash?

    The NAND flash boot mode is now supported in BF523/5/7 Rev 0.2+ and BF522/4/6 Rev 0.1+. Check the anomaly list for differences between revisions of silicon.

  • RE: adi_pwr service and VDDINT levels

    Hi,

    The accuracy was improved to +-5% on the BF523/5/7 and BF54x processors. Most newer Blackfin processors rely on external voltage regulators to supply VDDINT.

    Best Regards,

    Joe

  • RE: Booting from NAND Flash

    NAND Flash boot mode is functional in:

     

    BF523/5/7 – from 0.2 si rev

    BF524/4/6 – from 0.1 si rev

     

    This is doumented as Anomaly#05000382.

     

    -Anand

  • RE: Some troubles with softwarereset on BF527

    Hi Mathias,

    Which silicon rev are you using...? The bfrom_SysControl() firmware routine are functional from 0.2 silicon rev onwards for BF523/5/7

    Regards,

    Guru

  • Debugging Memory on Blackfin with external or dma modifications

    I am debugging an fpga memory connected to the 16bit  async bank1 of the adsp-bf523 blackfin processor.

    The memory is written in the fpga continuously with 16bit  values.

    When debugging the memory address with the  expressions window, the is a fault that…

  • SDRAM Timing

    Hello,
    i am using an ADSP-BF523 and an Elite SDRAM M12L64164A-5BIG2Y.
    The external busclock is 100MHz and the SDRAM-Timings are:
    *pEBIU_SDRRC = 0x612;
    *pEBIU_SDBCTL = EBCAW_8 | EBSZ_16 | EBE;
    *pEBIU_SDGCTL = PSS | TWR_2 | TRCD_2 | TRP_2 | TRAS_6 | CL_2 |…