• RE: Upgrade to VisualDSP 5.1.1 from 5.0.10

    Hi Tim,

    No, there should be no issues upgrading.

    Upgrading is a simple process. First, you can obtain the latest version of VisualDSP++ (5.1.2) from the VisualDSP++ Development Software Product Page here:


  • BF523 HOST Port interface(HOSTDP)


    I have a issue with regards BF523 HOST Port interface(HOSTDP).

    We are trying data transfer from host Device and blackfin and we find that the
    Host access and the Blackfin response is not matching with the working .
    This is same with both Acknowledge…

  • RE: What is the maximum DDR size that BF54x can support?


    What is the maxium Size support for BF523/5/7 and what is the maximium for BF522/4/6

    Data sheet and manual is a bit confusing .

    Thanking you

  • Debugging Memory on Blackfin with external or dma modifications

    I am debugging an fpga memory connected to the 16bit  async bank1 of the adsp-bf523 blackfin processor.

    The memory is written in the fpga continuously with 16bit  values.

    When debugging the memory address with the  expressions window, the is a fault that…

  • RE: adi_pwr service and VDDINT levels


    The accuracy was improved to +-5% on the BF523/5/7 and BF54x processors. Most newer Blackfin processors rely on external voltage regulators to supply VDDINT.

    Best Regards,


  • RE: Can BF52x processors be booted from NAND flash?

    The NAND flash boot mode is now supported in BF523/5/7 Rev 0.2+ and BF522/4/6 Rev 0.1+. Check the anomaly list for differences between revisions of silicon.

  • RE: Some troubles with softwarereset on BF527

    Hi Mathias,

    Which silicon rev are you using...? The bfrom_SysControl() firmware routine are functional from 0.2 silicon rev onwards for BF523/5/7



  • RE: Booting from NAND Flash

    NAND Flash boot mode is functional in:


    BF523/5/7 – from 0.2 si rev

    BF524/4/6 – from 0.1 si rev


    This is doumented as Anomaly#05000382.



  • SDRAM Timing

    i am using an ADSP-BF523 and an Elite SDRAM M12L64164A-5BIG2Y.
    The external busclock is 100MHz and the SDRAM-Timings are:
    *pEBIU_SDRRC = 0x612;
    *pEBIU_SDBCTL = EBCAW_8 | EBSZ_16 | EBE;
    *pEBIU_SDGCTL = PSS | TWR_2 | TRCD_2 | TRP_2 | TRAS_6 | CL_2 |…

  • RE: EXT_WAKE0 and EXT_WAKE1 of BF52x even number devices


    The reasons for two EXT_WAKE signals on the BF522/4/6 design are pin to pin compatibility with BF523/5/7 and in order to drive many inputs if desired. On EZ-Boards we try to make each signal available to demonstrate its assigned function if possible…