I'm a disty dedicated FAE for ADI, Now there is a issues about ADSP-BF522 in my customer:
They used ADSP-BF523 with Host DMA Download, it worked normally, and it's mass production;
When it's replaced by ADSP-BF522 with no change in the…
i have a Problem with the ADSP-BF523 that the 1V2 are causing an short circuit to the power supply.
I am using an external 3v3, 2v5 and 1v2 power supply.
Can you provide me an hint, what event can damage the dsp to show such a failure.
e.g. in the datasheet of BF-527, it sais the family has following processors:
but you said previously
"2) The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors belong to the same…
as VisualDSP++ 5.0 was released almost 3 years ago, there have been a number of bug fixes and improvements to the tools throughout the updates we have issues in that time.
Attached is the release note from VisualDSP++ 5.0 Update 8. This Release…
The anomaly will appear in Rev D of the BF522/4/6 list and Rev F of the BF523/5/7 list. We anticipate that the updated BF522/4/6 list will appear online at the end of the month and the BF523/5/7 list will go online sometime next month.
I'm not sure how useful this is but from VisualDSP++ Update 9 we added support for detecting when an application's stack size increases beyond its allocated size. You will find more information on page 9-8 of the attached Release Note for Update…
Could you explain me which way of PLL setting for BF527 is correct?
There is information:
"Note that the divisor ratio must be chosen to limit the system
clock frequency to its maximum of fSCLK. The SSEL value can be
dynamically changed without…
Although Blackfin processors have no power-up sequencing requirements, a silicon anomaly on existing ADSP-BF527 silicon revisions (0.0, 0.1 and 0.2) may lead to PLL issues when VDDINT is powered before VDDEXT. This very same issue is discussed…