I am having some problems getting my ADSP-21478 SHARC processor to execute a boot kernel in SPI Slave boot mode.
Initially, I performed some tests using the standard 21479.asm boot kernel, but for debugging purposes I created a custom boot kernel…
I'm using host processor to boot ADSP-21478. I have a problem because i need to add delays between sent words to boot DSP correctly. I would like to use MISO pin for handshake, but the state of this pin remains unchanged (pullup and pulldown resistors…
Want to use the IDP of SHARC to combine 8 I2S input channels to generate one TDM output.
I am trying to use the simulator for the 21478 to verify the SPORT DMA with streams. I modified one of my existing programs I originally wrote for the 21065L. Before I modified it, I checked it again using the simulator in VisualDSP 5.1 and it worked…
In the Multi_Iteration_Mode example
TCB block for the fir accelerator is mentioned in one order and the TCB block defined in its reverse order.
And it will work only if we follow the code similarly, why we have to follow in this order??
The internal ROM is not user programmable. It is factory programmed, it requires a minimum order and there is an NRE associated for custom ROM programmed parts. For further details please contact your local sales representative.
FFT Accelerator on ADSP-SC58x/ADSP-2158x is a completely new design as compared to the FFT accelerator on ADSP-214xx processors. The major differences/features of the FFT accelerator on ADSPSC58x/ADSP-2158x are:
Customer ask some questions.
Right now we have plenty of software for ADSP-21489, but it’s quite hard to port it to ADSP-SC573 family. Code itself
is 99% C and C++.
Does family ADSP-SC573 have interface with external static memory like AMI for ADSP…