• Minimum SCLK in ADSP-21562


    What is the minimum SCLK for the ADSP-21562, I can work with?

    Can I program fCCLK to 200 or 100 MHz in ADSP-2156x processors

    best George

  • RE: ADSP-21569 AEC tuning GUI


    What is going on?

  • Frame Sync Error when using ADSP-21569


    In the Hardware reference of ADSP-215**, there are descriptions about "Frame Sync Error" and Interruption of this error.

    So, could you tell me what happen when "Frame Sync Error Interrupt" is occurred?

    And There is "MASK"…

  • FAQ: ADSP-21569 SPI Host example

    Attached is the ADSP-21569 SPI Host example and the connection diagram to boot the another DSP via SPI slave boot mode. This code is verified between two ADSP-21569 Ez-kits.

    Normally, all the slave booting process is done as, the Host Application would…

  • Bare Metal SDK Framework in ADSP-2156x

    Kindly let us know your feedback for below queries in 'Bare Metal SDK-Rel2.1.2 Framework'.
    1. Can we use Bare Metal framework for ADSP-2156x processor series. Is this framework processor independent?
    2. We understand Bare Metal framework is specific…
  • EEPROM boot in ADSP-TS201 multiprocessor configuration

    ADSP-TS201 I have a question about EEPROM boot in a multiprocessor configuration.

    I'm trying to understand the boot sequence for a multiprocessor configuration by comparing the ADSP-TS201 datasheet,

    the TigerShark architecture AP, EE and the files…

  • RE: ADSP-SC573 with AD73360 via SPORT


    We understood that after adding proper SPU IDs in your application, the DMA transaction issue got resolved in your side.

    Best Regards,

  • ADSP-2156x 120-Lead LQFP reference schematic

    There doesn't seem to be any hardware reference design for the ADSP-2156x SHARCS with the 120-Lead LQFP package.

    Specifically, for power supply bypassing.

    In the schematics for the 21569 EZ-Kit etc. the bypassing scheme is best described as.... random…

  • ADSP-21565 max CLKIN0 frequency


    The data sheet for the ADSP-21565 specifies that the max CLKIN0 freq is 30MHz, however I would like to ask whether there would be any issues if I was to drive it with at 40MHz (as I have done previous (legitimately) with SHARC DSP processors such…

  • ADSP-21569 API Documentation

    I would like to use the provided hardware drivers for the ADSP21569. For example: In the provided examples the functions defined in "adi_sport_2156x.h" are usedto set up serial comunication such as TDM. I would like to do so aswell.