• Frequency Hopping Example (RX-TX) for more than 8 profile ( adrv9361-z7035 & Adrv1crr-bob)

    Dear all,

    Hopping IP has inserted in HDL_2019_r2 for adrv9361-z7035 and adrv1crr-bob . and I checked for 8x profile (Rx & Tx ) and its working correctly. Each profile covers 50MHz bandwidth ( total 8*50MHz).My application requires to scan wide bandwidth…

  • Problem in calculating Peak Search Algorithm for RF Signal targeting ADRV9361-z7035

    Dear All,

    I implemented a peak search algorithm in HDL reference design  targeting platform is ADI ADRV9361-z7035 . Let me first talk about my algorithm.

    1-  I am calculating bin from Xilinx FFT core ( 8192 points ) inserted in ADC path

    2- Then I slice…

  • Add ILA in adrv9361-z7035 no-OS project


    I would like to know how is the correct way to incorporate an IP ILA to the HDL Reference Design.

    In my case, add the ip through the GUI. I then generated the bitstream and exported the hardware adding the bitstream.

    My problem is that when I open…

  • ADRV9361 transceiver ADC Problem


    Hope you are doing well.

    I am trying to implement QPSK modulation on ADRV1-9361-Z7035.

    At transmission side, my signal is modulated correctly giving all four-phase transitions according to data pattern when visualized on ILA as shown in figure…

  • RE: dma-axi-dmac module failed to load on adrv9361-z703 (ADRV9361)

    Are you still facing the issue? If yes, then you can post a new query in the below forum:


  • Pynq support for ADRV9361/64 Devices

    I want to know regarding the support for Pynq package in ADRV9364/61 devices. Can I use pynq  to build projects ON ADRV9361/64 which are based on z7020 and z7035 fpga's as suggested here ?

  • RE: Recording RF spectrum to IQ file using ADRV9361-z7035

    Are you using Linux drivers for configuring the chip?

    You can use the IIO scope tool to capture the RX data in IQ format. refer to below link:


  • Clock and reset in adrv9361-z7035


    I want to test my simple counter design on the adrv9361-z7035 board FPGA without using the reference design they give me.
    In this case I want to use a clock signal and a reset signal. But I can not understand which is the pin that I should relate…
  • Pin reading from adrv9361-Z7035 HDL design in bash script

    I want to read a pin from HDL design in the bash script given below in order to make a decision. Guide me  about the procedure:

    cd /sys/bus/iio/devices/iio\:device1/
    for i in {1..8..1}
    echo $((650000000 + $i * 100000000)) > out_altvoltage1_TX_LO_fr…

  • Synchronize Rx and Tx Fast Lock profile ADRV9361-z7035

    Dear ,

    I implemented different signal processing block within Reference design . I am facing a issue. Let me elaborate following

    1- Rx Profile 0 : RF BW 56 MHz , LO 2428 MHz

        Rx Profile 1 : RF BW 56 MHz , L0  2484 MHz

    The above are the settings of ADRV9361…