• RE: Configuring devicetree for picozed sdr

    Don't use auto generated devicetree files at all. zynq-picozed-sdr*.dts files only exists on older release branches.

    On the latest release they are called zynq-adrv9361-z7035*.dts.

    the .dtsi files are just common includes for the .dts files.


  • RE: Required detail on 33.33 MHz clock oscillator specification for Z7035 FPGA


    I required an information for FPGA clock(33.33 MHz), which is given in ADRV9361-Z7035 for zynq PS clock, the above link you have sent is for AD9361 TCXO.

    In ADRV9361-Z7035 , there is one clock oscillator of 33.33 MHz for FPGA PS clock,(connected…

  • BOM list of ADRV9361-Z7035


    Could I have the BOM list of ADRV9361-Z7035 evaluation board?


  • RE: ADRV9361z7035 on ADRV1CRR-BOB, reference design

    Both should be on the SD card:

    zynq-adrv9361-z7035-bob (LVDS)



  • RE: ADRV1CRR-FMC Ethernet and PCIe


    Sorry for the late reply.

    The ADRV1CRR-FMC is meant to be used with the RF SOM, so all the docs should be pointed to check for either ADRV9364-Z7020 or ADRV9361-Z7035

    For HW stuff a link is:


  • Issue in GNU radio FMCOMM block installation in windows for ADRV9361-Z7035


    I have ADRV9361-Z7035 evaluation board with ADRV1CRR-BOB carrier . I have followed below instructions in order to install FMCOMMS2/3/4 source and sink block to GNU radio in windows environment.


  • ADRV9361-Z7035-Clock routing

    Hi everyone,

    I'm trying to understand the clock routing in reference design of ADRV9361-Z7035. I found clock routing diagram for ZC706 and fmcomms2 here. Please help me understand clock routing for ADRV9361-Z7035. 


  • adrv9361 RX sample rate

    Hi , 

    I'm using the ad9361-iiostream.c example .

    I've changed the sample rate to 5Msps with 1Msp buffer size and expected to get at least 5 "buffer_refill"s every 1 second.

    Unfortunately i get only 2 buffer refills every second (~2.5Msps…