• ADRV9009 does not enumerate axi-adrv9009-tx-hpc and axi-adrv9009-rx-hpc during boot

    STEP 1:

    Using the ADRV9009 evaluation board with a ZCU102 carrier, I was able to port the example Vivado project to Petalinux. I am using the ADI kernel in Petalinux so that I have access to all the ADI IIO device drivers and libraries. This boots successfully…

  • Operating the ADRV9009 at 208MHz

    I currently have a working solution consisting of three ADRV9009 devices clocked by an HMC7044. I have the sample rate set to 245.76MSPS. I am currently using the CPLL for the RX and OBS RX and QPLL0 for the TX. I am using ADI kernel 2019_R2 branch.

    …

  • ADRV9009 control in "ADRV9009 + ZCU102"

    Hello,

    I use ADRV9009 and ZCU102.

    I control the ADRV9009 via the IIO Oscilloscope.

    But can I adjust the sample rate for the ADRV9009 on an IIO oscilloscope? (Rx path)

    I need tuning for 30.72 / 61.44 / 122.88 / 245.76MHz and Data Capture for it.

    Thank…

  • ADRV9009 axi_adrv9009_xcvr Change to CPLL/QPLL1

    Hello

    I have custom hardware with three ADRV9009 devices connected to a Xilinx Zynq MPSOC ZU6 device. I am using the hdl_2018_R2 components in my block design to create the JESD204B interface to the ADRV9009.

    I have initially copied over all the settings…

  • How to configure device tree to use more than one ADRV9009

    Hello

    I have custom hardware that has three ADRV9009 devices on it. These devices are clocked by an HMC7044. I have confirmed that the HMC7044 is outputting the correct clocks. I am using Vivado 2018.2 to generate the firmware, Petalinux 2018.2 to generate…

  • DisplayPort output of ADRV9009 SOM (adrv9009-zu11eg)

    I have the ADRV9009 SOM, and can boot up and run IIOscope remotely.  However, I'd also like to use the DisplayPort video output.  I've connected a monitor, and USBC keyboard/mouse.  I've also run these commands, per  https://wiki.analog.com/resources…

  • ADRV9009 4T4R non-OS example to sync multiple ADRV9009

    Dears,

    My Customer is working on sync 2 ADRV9009 with Non-OS examples from Git. It worked well one by one. But could not sync correctly with two parts together, always the second one failed setup. Do you have some 4T4R initialization examples Non-OS…

  • Altera HDL reference for 4x Adrv9009 (at least 2x Adrv9009) ?

    Hi ,

    I want to know the newest update regarding of "Altera HDL" to support 4xAdrv9009" (at least to support 2x Adrv9009)  from ADi support teeam?  What's the current status about this feature? 

    If it's available somewhere, which would…

  • RE: ADRV9009 RX data width

    1. The data before the Transport layer is frame data. ADC_DATA[0/1] corresponds to I/Q for RF channel 0 and ADC_DATA[2/3] correspond to I/Q for RF channel 1.

    2. You only need two GTX transeiver channels for RX data in FPGA, yes.

    Regards,

    Adrian

  • ADRV9009 SPI initial error: adrv9009 spi32766.1: ERROR: 1: ADIHAL: SPI Failure

    I am using zcu102+adrv9009. When booted from SD using the given linux, sometimes the adrv9009 can not initial succussfully, chocked the SPI processing, showing errors below. Sometimes it goes OK and the ADRV9009 can work exactly. What is the wrong?

    …