• ADRF6755

    Hi Guys,

    I have a question for ADRF6755.

    If the IQ input Vbias is over than 0.5V(0.6V) and it could be worked as well?

  • ADRF6755 PFD frequency.


    1)  What is the maximum limit for PFD frequency in ADRF6755 

    2) Is it compulsory to use frequency doubler and R/2 and 5-bit R divider.

  • ADRF6755 LOMON output


    About the "controls the LO monitor outputs" and the "LO output circuits" at the ADRF6755,

    in the datasheet 37 page @ ADRF6755,

    " If not used, these outputs should be tied to REGOUT."

    and 29 page,

    "Register CR27…

  • ADRF6755 THETA(ja)


    I can't find THETA(ja) for  ADRF6755, could you please provide it to me ? 

    Many thanks,


  • ADRF6755疑问

           专家你好  :现在我对6755的文档有些疑问,

    1   文档上说基带的四路输入必须通过差分源驱动,标称电平是0.9Vp-p差分,     每个引脚是450mv,应偏置500mv的DC共摸电平,疑问是四路必须是没路450mv的交流电平么?

    2    6755的在输入信号时10dbm差分信号的情况下,本振按照文档给的能抑制多少?输出的信号幅度是多少(6755增益全开)

    3增加新的发现:在调试的过程中发现6755产生了交调产物,我的基带信号是固定的100M,通过调节6755得到我想要的频率,在我要得到40M 的时候…

  • ADRF6755 RF output


    After setting the attenuation value to 0 dBm, I am getting -24dBm for 1GHz.I have attached schema and other details. If any suggestion you have, let me know.

    1)REFF input CLK And PFD set -40Mhz (/2,bubbler&5bit Rdivider all are disabled.)


  • ADRF6755 RF - output

    Hi ,

    After setting the attenuation value to 0dBm by writing 0x00 to  CR30 register still i am getting -60dBm for 2GHz,Please suggest if any settings required to bring the signal level to 0dBm.

  • ADRF6755 IQ Inputs levels

    I'm trying to understand what kind of inputs the ADRF6755 requires. That what the data sheet says:


    The baseband inputs, QBB_P, QBB_N, IBB_P, and IBB_N, must be driven from a differential source. The nominal…

  • ADRF6755 Differential termination

    Hi Team,

    DO you have any Synthesizer IQ Modulator Interface termination and LPF calculation Excel spreadsheet or Notes?.

    Our DAC Output Common Mode voltage = 0.5V to .7Vmax,DAC Full Scale output current = 1.125 to 3mA,sampling frequencies ranges from 2MSPS…

  • Problem communicating with ADRF6755

    I am working on an interface to configure ADRF6755 on its I2C bus, and for that I use a FPGA from Altera (Cyclone IV EP4CE22) to generate the SDA and SCLK signals to the ADRF (to its pin 29 and 30). I followed the configuration sequence pointed out in…