I have a standalone application where I need 5 voltages to come up to power an FPGA & some front end circuitry. The ADP5052 looks like a good candidate, but I could also use the ADP5050 as it is pin-for-pin compatible outside of the I2C bus. The ADP5050…
I have a question ADP5052 layout.
In ADP5052 DS is,
Exposed Pad connect to 30pin PGND.
In ADP5052 Simulation tool Excel file is ,
No connect Exposed PAD to 30pin PGND.
Which is better for ADP5052 layout?
(I think both are no problem.)
My system ADP5052 CH3 provide 1.5V to DDR3 VDDQ/VTT(1.5V) use, but I found just ADP5052 CH3 output with DDR3 VDDQ/VTT 1.5V together, ADP5052 CH3 output voltage down to 1.39V~1.4V. ADP5052 can give DDR3 VDDQ and VTT 1.5V power source? DDR3 VTT…
Why would I be getting 0.8V output on channel 3 of the ADP5052. I have configured it to match the example given in the datasheet. (Channel 3 is located at the bottom right hand corner. U4 and U5 are seperate chips)
Also, why is the example in the datasheet…
The ADP5052 be used in FPGA, design in DSO products,
We to add the hot wind into adp5052,then the adp5052 will shutdown as data sheet mentioned
If the ADP5052 junction temperature exceeds 150°C, the thermal shutdown circuit…
Please refer to link below for the layout of CH3 and CH4 of ADP5052 designed for .
Evaluation Board for the ADP5050/ADP5052 5-Channel Power Management Unit (PMU) [Analog Devices Wiki]
I found the cause of my issues and it was unrelated to factory programmable options.
With that said, does "there is only one ADP5052 IC model released" mean that nobody has ever ordered the ADP5052 with any of the factory programmable options other…
Dear Engineering Zone!
I have a question regarding power derating of the ADP5052.
In the datasheet there is no information about this matter. Also I tried to explore the behavior of the ADP5052 through the ADP505x_BuckDesigner tool. If I begin to increase…