Hi all,

I am trying to simulate ADP5052 channel 1 and 2 in LTspice there is more one pin on the simulation symbol called Rlim. But there is no pin like that in real IC. What is this Rlim pin on the simulation circuit IC of ADP5052. 

Hello Everyone, 

I would like to know what is the recommended buck regulator channel sequence  for ADP5052.

Why would I be getting 0.8V output on channel 3 of the ADP5052. I have configured it to match the example given in the datasheet. (Channel 3 is located at the bottom right hand corner. U4 and U5 are seperate chips)

Also, why is the example in the datasheet…

Hi

I have a question ADP5052 LDO.

When LDO is not used in ADP 5052,
Is PVIN 5 OK even with OPEN?
(EN pin is connected to 0 V)

Best Regards

HOD

Hi

I have a question ADP5052 Layout.

It is written that inductors and SW terminals are connected to the data sheet with the shortest thick pattern

In the actual pattern diagram, connections with 3ch and 4ch inductors are narrowing.

Power supply design…

Dear Engineering Zone!

I have a question regarding power derating of the ADP5052.

In the datasheet there is no information about this matter. Also I tried to explore the behavior of the ADP5052 through the ADP505x_BuckDesigner tool. If I begin to increase…

Hi

I have a question ADP5052 layout.

In ADP5052 DS is,

Exposed Pad connect to 30pin PGND.

In ADP5052 Simulation tool Excel file is ,

No connect Exposed PAD to 30pin PGND.

Which is better for ADP5052 layout?

(I think both are no problem.)

Hi Sir

The ADP5052 be used in FPGA, design in DSO products,

We to add the hot wind into adp5052,then the adp5052 will shutdown as data sheet mentioned

THERMAL SHUTDOWN

If the ADP5052 junction temperature exceeds 150°C, the thermal shutdown circuit…

Dear Sir:

I tested ADI ADP5052 demo board "ADP5052-EVALZ to found out PWRGO (Power Good) demo board and datasheet is somewhat different. pls see below:

Q1: the datasheet Page4 "Table 1."Power Good If CH1 Output Normalcy, then VPWRGD_high…