• RE: adp5052 VREG Problem

    Hi gcentinkaya,

    Possible reason is damage or manufacturability issue. We would always recommend that before you make custom design, start with our demo board, modify from there, compare performance. Also, please do not connect anything to this pin. 

  • RE: ADP5052 Simulation Individual channels

    Hi 

    The model is currently optimized in simulating the operation of either CH1 or CH2 at steady state.

    Please perform bench verification for the different timings for start up 

    Regards

  • ADP5052 internal regulator VREG and VDD problems

    I have a design that we just got back from a CM that is not working.  We reused the ADP5052 portion that we have used on 3 other designs before that worked great.  On the new board the VREG is reading 1.8 instead of the 5.1 we read on an old design that…

  • ADP5052

    Why would I be getting 0.8V output on channel 3 of the ADP5052. I have configured it to match the example given in the datasheet. (Channel 3 is located at the bottom right hand corner. U4 and U5 are seperate chips)

    Also, why is the example in the datasheet…

  • ADP5052 LDO

    Hi

     

    I have a question ADP5052 LDO.

     

    When LDO is not used in ADP 5052,
    Is PVIN 5 OK even with OPEN?
    (EN pin is connected to 0 V)

     

    Best Regards

    HOD

  • ADP5052 Layout

    Hi

    I have a question ADP5052 Layout.

    It is written that inductors and SW terminals are connected to the data sheet with the shortest thick pattern

    In the actual pattern diagram, connections with 3ch and 4ch inductors are narrowing.


    Power supply design…

  • ADP5052 power derating question

    Dear Engineering Zone!

    I have a question regarding power derating of the ADP5052.

    In the datasheet there is no information about this matter. Also I tried to explore the behavior of the ADP5052 through the ADP505x_BuckDesigner tool. If I begin to increase…

  • ADP5052 GND Layout

    Hi

    I have a question ADP5052 layout.

    In ADP5052 DS is,

    Exposed Pad connect to 30pin PGND.

    In ADP5052 Simulation tool Excel file is ,

    No connect Exposed PAD to 30pin PGND.

    Which is better for ADP5052 layout?

    (I think both are no problem.)

  • ADP5052 Thermal Shutdown

    Hi Sir

    The ADP5052 be used in FPGA, design in DSO products,

    We to add the hot wind into adp5052,then the adp5052 will shutdown as data sheet mentioned

    THERMAL SHUTDOWN

    If the ADP5052 junction temperature exceeds 150°C, the thermal shutdown circuit…

  • ADP5052 PWRGD Question

    Dear Sir:

    I tested ADI ADP5052 demo board "ADP5052-EVALZ to found out PWRGO (Power Good) demo board and datasheet is somewhat different. pls see below:

    Q1: the datasheet Page4 "Table 1."Power Good If CH1 Output Normalcy, then VPWRGD_high…