• EVAL-ADP5040 Docs


    I wanted to use the ADP5040 Eval board, and unfortunately there is no documentation about this board avaiblable.

    Can someone help me out?

    Kindly regards

  • RE: ADP5040 GND layout.

    Dear Mr. Jess

    Thank you very much for you careful explain.

    "In general, it is not advisable to connect the PGND and AGND directly on the top layer to prevent the noise coming from the power stage to appear in the analog section."

    It is one…

  • ADP5040无输出


  • 12V input voltage version of ADP5040?


    Is there available 12V input voltage version of ADP5040 PMU?

    If not could you propose equivalent PMU for AD9364 RF transceiver, so PMU which max. input voltage would be 16V.

  • RE: 全面了解基于射频捷变频收发器AD9361的软件定义无线电解决方案


  • AD9361 + ADP1755


    AD9361 datasheet 有標明1.3V range 應該在1.267V~1.33V, tolerance 大概2.5%左右~~

    假設參考ADI 建議的 ADP1755~~

    就datasheet 所描述, 是否所有誤差的產生都在外部電阻, ADP1755 本身的ADJ output沒有任何誤差???


    另外, power 文件有提到, 除了ADP1755 LDO 之外, 也可使用switching 的方式~~例如ADP5040~~

    但AD5040的誤差更大, 應該無法達到AD9361的標準…

  • AD9361 Data Interface Question


    I am trying to understand the data interface to this chip.  When in CMOS, dual port, half duplex mode; the BBP drives the ENABLE and the TXNRX lines.  My understanding is that it asserts the enable high with TXNRX low to request any received data…

  • Maximum data rate

    We are using fmcomms2 boards to set up LVDS Full Duplex TDD.

    We don't understand how the maximum data rate matches with the reference manual UG763 and other sources.

    It says in the following two links (and there is also a limit in software) that…

  • AD9361 Test Specification


    I am working on a picozed sdr2 rev. e. I am trying to verify the performance of the ad9361 by doing the test measurement for 2.4GHz for the transmit chain based on the page 4 of the datasheet as attached. I will like to clarify on that page under…