• ADP2164 and ADP2164-1.8

    Hi,

    I am using one of regulator ADP2164 in my circuit to generate 1.8 V from 3.3 V input. unfortunately i mounted ADP2164ACPZ-1.8 instead of ADP2164APZ. As per my circuit i used feedback resistors to adjust and i mounted the which has fixed output voltage…

  • About ADP2164

    Hi,

    I have some questions about ADP2164.
    In my system, it requres to use different power rails for VPIN and PVIN like the attached file.
    These two inputvoltage are not applied to ADP2164 at the same time, there are some delay times between 5V_1 and 5V_2…

  • About PGOOD of ADP2164

    Hello!

       I just want to make the PGOOD pin be high.

       http://www.analog.com/media/en/technical-documentation/data-sheets/ADP2164.PDF

       The EN pin is a slope signal (high is 4.1646V and low is 4.076V) with a period of 1.8ms.

       SW is rectangular wave with a period…

  • About Exposed Pad of ADP2164

    Hi,

    My customer want to know that the Exposed Pad and PGND/GND of ADP2164 are connected internally or not.
    According data sheet of ADP2164, there was no information of that.  Could you please let me know if you have this answer.

    Best regards,

    Makio

  • ADP2164 PGOOD outout very unstable

    Hello

    We are using the ADP2164 to regulate 5V down to 3.3V. See images for the schematic,

    We are experiencing that the PGOOD output is not behaving as expected (See image: green=PGOOD, red=5V, blue= 3.3V)

    PGOOD is not behaving in a digital way and it…

  • ADP2164 Forced continous switching

    I would like to free-run the ADP2164 at ~650Khz but do not want it to go into pulse skip or burst mode with no load.

    I can calculate the RT value but the question is with the SYNC pin.

    Can I tie the Sync pin low to do this or is there another way to…

  • About EN pin on ADP2164

    Hi there.

    I have something to make sure about EN pin of ADP2164.

    http://www.analog.com/media/en/technical-documentation/data-sheets/ADP2164.PDF

    I just want to know the enable/disable area.

    I drew a diagram, so please check the attached file.

    Please…

  • 怎样使ADP2164的PGOOD输出高电平

    我的目的是使得ADP2164的PGOOD管脚输出高电平。

    EN管脚使用示波器测得其为斜坡信号(上下峰均为4.1646V和4.076V)

    VIN/TRK/SYNC/PVIN是4.9mV,RT/GND/PGND是0V,EN是三角波,周期1.8ms,高低电压分别为4.2V和4.1V,SW是高低电平分别为5V和0V、周期1.6us矩形波。FB是602mV,PGOOD为135mV。

    读数据手册查找问题的过程中,有两个问题:

    (1) FB明明在600mV+-10%的范围内了,PGOOD应该输出高电平

  • Requesting for clarification on SYNC pin of ADP5054 and ADP2164, on high priority

     Requesting for clarification on SYNC pin of ADP5054 and ADP2164, on high priority.zip

    Hi All,

    I have a query wrt the SYNC pins of ADP5054 and ADP2164.

    In the Power Section we are deriving 4 voltage nets required for AD9364 - 3.3V, 1.8V, 1.3V_A Supply…

  • About tracking function.

    Hi there,

    I checked the tracking function on ADP2164 evaluation baord.

    But the resut was a little bit diffrent from what I expected.

    Please look at the attached file and give your opinion about this resutl.

    ( I guess it was affetected by resistance…