• ADP2164 PGOOD outout very unstable

    Hello

    We are using the ADP2164 to regulate 5V down to 3.3V. See images for the schematic,

    We are experiencing that the PGOOD output is not behaving as expected (See image: green=PGOOD, red=5V, blue= 3.3V)

    PGOOD is not behaving in a digital way and it…

  • About Exposed Pad of ADP2164

    Hi,

    My customer want to know that the Exposed Pad and PGND/GND of ADP2164 are connected internally or not.
    According data sheet of ADP2164, there was no information of that.  Could you please let me know if you have this answer.

    Best regards,

    Makio

  • Requesting for clarification on SYNC pin of ADP5054 and ADP2164, on high priority

     Requesting for clarification on SYNC pin of ADP5054 and ADP2164, on high priority.zip

    Hi All,

    I have a query wrt the SYNC pins of ADP5054 and ADP2164.

    In the Power Section we are deriving 4 voltage nets required for AD9364 - 3.3V, 1.8V, 1.3V_A Supply…

  • RE: About ADP2164

    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
  • RE: ADP2164 and ADP2164-1.8

    Hello,

        I am also following the same regulator (ADP2164 + ADP1755) schematic (almost same) for AD9361 but at the Tx output i am getting 45dBc spurious @ 1.2MHz offset. How to suppress this spurious? For ADP2164 switching frequency is 1.2MHz.

  • RE: ADP2164 Forced continous switching

    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
  • About PGOOD of ADP2164

    Hello!

       I just want to make the PGOOD pin be high.

       http://www.analog.com/media/en/technical-documentation/data-sheets/ADP2164.PDF

       The EN pin is a slope signal (high is 4.1646V and low is 4.076V) with a period of 1.8ms.

       SW is rectangular wave with a period…

  • 怎样使ADP2164的PGOOD输出高电平

    我的目的是使得ADP2164的PGOOD管脚输出高电平。

    EN管脚使用示波器测得其为斜坡信号(上下峰均为4.1646V和4.076V)

    VIN/TRK/SYNC/PVIN是4.9mV,RT/GND/PGND是0V,EN是三角波,周期1.8ms,高低电压分别为4.2V和4.1V,SW是高低电平分别为5V和0V、周期1.6us矩形波。FB是602mV,PGOOD为135mV。

    读数据手册查找问题的过程中,有两个问题:

    (1) FB明明在600mV+-10%的范围内了,PGOOD应该输出高电平

  • About EN pin on ADP2164

    Hi there.

    I have something to make sure about EN pin of ADP2164.

    http://www.analog.com/media/en/technical-documentation/data-sheets/ADP2164.PDF

    I just want to know the enable/disable area.

    I drew a diagram, so please check the attached file.

    Please…

  • AD9364 Power supply query

    Hi,

    Currently we are designing a custom board based on AD9364 chipset. I had referred the Evaluation board for the power supply section. The EV board contains the 3.3V to 1.8V conversion  using ADP2164 chipset which is 4A capable device.

    Also there are…