Hi Prakash BJ,
The AVDD and DVDD supply pins of the AD9959 draws a maximum of 325mA when all channels are turned on.
The 800mA maximum output current of the ADM7160 can only supply up to two DDS chips.
There are higher current output LDOs such as the…
Our customer purchaced 2-units of AD9649-20EBZ.
The customer saids that the LDO of U105 is different from schematic Rev.B .
ADP1706ARDZ-1.8 is mounted as U105, this LDO is a same as U104.
Both of t he 2-units are the same.
I have had the…
I am trying to consider DC-DC regulator to the power of analog circuit with a high sensitivity. As a result of reading the attached file, I want to consider the ADP2114/2116.
1. Using single mode, it outputs 4A/6A. For example, by connecting
According to the document UG-551, if it's support the output jitters to 0.4 UI while external clock input (@ 8Gbps,40MHz) in mode 5 ?
Thanks in advance.
I am trying to understand the data interface to this chip. When in CMOS, dual port, half duplex mode; the BBP drives the ENABLE and the TXNRX lines. My understanding is that it asserts the enable high with TXNRX low to request any received data…
We are using fmcomms2 boards to set up LVDS Full Duplex TDD.
We don't understand how the maximum data rate matches with the reference manual UG763 and other sources.
It says in the following two links (and there is also a limit in software) that…
Many thanks for this.
After a lot of wire mods, I got the AD9125 eval board working with the tester. I am able to read and write to the device and get a signal on the DAC outputs using the NCO. I tried the Parallel port, but this was unsucessfull…