I want to use ADN4670 in my project but I have 3 questions about its functionality.
1) According to the datasheet, ADN4670 receives 12 bits through serial communication to program the device. So I need to push to high the EN pin, generate clock and send…
Hi,
Is it possible to input a clock to ADN4670 which has a duty cycle of say 20%. e.g. a 10MHz square wave which has a high time of 20ns? At the outputs of course I require the same duty cycle signal.
In the datasheet Table3: tDUTY is given as 45-55…
I need to have all the outputs enabled with ADN4670 on Power-On and later through programming, I want to disable some of the outputs.
In the programming section of datasheet it is mentioned that this is possible, provided the inputs EN and SI are…
You may want to look at the ADN4670 also.
Hi Gavin,
Follow the JEDEC standard for the ADN4670. There is a link to the standard on the website link below.
Package Resources | Design Center | Analog Devices
Regards,
Jason
Bedoustani,
Have you looked at our clock portfolio at analog.com?
https://www.analog.com/en/parametricsearch/11074#/p4481=|Delay|Distribution|Divider|Programmable%20Oscillator|Signal%20Generator|Synchronization&p4482=LVDS
Depending on the number of…
Hello Tak-san,
Can I confirm that for this application, you are concerned with additive phase jitter (phase noise integrated across a frequency range of e.g. 12kHz to 5 MHz, for a carrier freq of 20 MHz)?
Unfortunately we do not have this jitter data…
Hello Niulian,
If I understand correctly, you want to buffer the LVDS outputs from the FPGA in order to drive them across a longer distance?
What distance do you want to drive across, and at what clock/data speeds? What is at the receiving end?
The…
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