• Pin configuration about ADN4668 LVDS Rx when power-off

    Hi,

    Currently, I have following questions . Can you confirm it?

     

    1) When ADN4668 is power-off, how is phy configured LVDS Rx side in ADN4668? For example, is that a Hi-Z?

     

    2) If 1) is not Hi-Z, when there is DC at LVDS Rx side, we want to know whether…

  • RE: About unused LVDS pin of ADN4668

    To avoid chatter on the output, leaving the input open is best. The ADN4668 has open circuit failsafe, so the output state will stay in logic 1 state.

    By contrast, adding termination to the input but not driving it, will result in an indeterminate state…

  • Slow Risetime Driving IO_UPDATE on AD9915 Eval Board

    I am using an ADN4668 driven by an ADN4467 to send the IO_UPDATE siignal to the coaxial IO_UPDATE input on the AD9915 Eval Board. The measured risetime is 2 ns. The LVDS signal at the input has a risetime of about 0.5 ns. The spec sheet for the ADN4668…

  • RE: any solution for lvds driver from FPGA

    Hello Niulian,

    If I understand correctly, you want to buffer the LVDS outputs from the FPGA in order to drive them across a longer distance?

    What distance do you want to drive across, and at what clock/data speeds? What is at the receiving end?

    The…

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