• About unused LVDS pin of ADN4668

    I would like to confirm about unused LVDS input pin of ADN4668.

    What is the recommended state? (Open or termination?)

    Best regards,

    Yutaka

  • Pin configuration about ADN4668 LVDS Rx when power-off

    Hi,

    Currently, I have following questions . Can you confirm it?

     

    1) When ADN4668 is power-off, how is phy configured LVDS Rx side in ADN4668? For example, is that a Hi-Z?

     

    2) If 1) is not Hi-Z, when there is DC at LVDS Rx side, we want to know whether…

  • ADN4662/ADN4664 High-Z O/P's on Powerdown

    While the ADN4668 (4-ch) features dedicated Enable pins, neither the ADN4662 (1-ch) nor the ADN4664 (2-ch) has any.

    Nevertheless, both their datasheets report "High impedance outputs on power-down" as a feature in the first page, but no further mention…

  • Slow Risetime Driving IO_UPDATE on AD9915 Eval Board

    I am using an ADN4668 driven by an ADN4467 to send the IO_UPDATE siignal to the coaxial IO_UPDATE input on the AD9915 Eval Board. The measured risetime is 2 ns. The LVDS signal at the input has a risetime of about 0.5 ns. The spec sheet for the ADN4668…

  • TAGS LIST: Interface and Isolation

    LTM2894
    LTM2895
    LTM9100
    LTM2885
    LTM2881
    LTM2882
    LTM2883
    LTM2884
    LTM2893
    LTM2886
    LTM2887
    LTM2889
    LTM2892
    LTC1694-1
    LTC4300
    LTC4310
    LTC4302
    LTC4305
    LTC4304
    LTC4303
    LTC4306
    LTC4307
    LTC4307-1
    LTC430…
  • RE: any solution for lvds driver from FPGA

    Hello Niulian,

    If I understand correctly, you want to buffer the LVDS outputs from the FPGA in order to drive them across a longer distance?

    What distance do you want to drive across, and at what clock/data speeds? What is at the receiving end?

    The…

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