Hello Maurizio,
Thank you for the explanation. If I understand correctly, the board in design may be SPI master or slave (Potentially ADN4696E for the interface) that will connect to one other board (either a master or a slave, with ADN4661/ADN4662)…
For the ADN4662, where in the data sheet can I find the phase jitter? I'm trying to use a part that induces minimum error while passing this trigger signal through it. We need to characterize the propagation delay through our signal chain as accurately…
Hi,
ADN4662 has failsafe output state (output stays stable logic high) for only one condition, open circuit. With 100 Ohm termination across the inputs, the input is not open circuit, but looks similar to a short circuit with ~0V differential. The receiver…
Hi All,
My customer is considering using ADN4662 LVDS receiver and ADN4661 transceiver for his new design. Its cable distance will be 25m long.
Data Rate will be 25MHz. Matching between cable impedance and termination is most important, I believe.
Hello Niulian,
If I understand correctly, you want to buffer the LVDS outputs from the FPGA in order to drive them across a longer distance?
What distance do you want to drive across, and at what clock/data speeds? What is at the receiving end?
The…