• Jitter specifications of ADN4661

    Hello,

    We tried to use the ADG3241 as the clock buffer supplied to the AD9257.

    But the jitter is large, so we should consider immediately a different device.

    We expect that the ADN4661 can use instead of the ADG3241.

    Please  let me know jitter value…

  • ADN4661 LVDS time jitter

    Hi All,

    One of my customers would like to know the time jitter for the ADN4661 LVDS driver, but not indicated on the data sheet.

    Could you suggest us with it?

    Thank you for your help.

    Ricky

  • ADN4661/ADN4662 with 25m long cable

    Hi All,

    My customer is considering using ADN4662 LVDS receiver and ADN4661 transceiver for his new design. Its cable distance will be 25m long.

    Data Rate will be 25MHz. Matching between cable impedance and termination is most important, I believe.

  • RE: Are ADN4696E compatible with ADN4662?

    Hello Maurizio,

    These devices are designed for different applications, the ADN4696E/ADN4697E are designed for multipoint LVDS communication (M-LVDS) and the ADN4661/ADN4662 for point-to-point LVDS.

     

    What application would you wish to connect these…

  • RE: AD9747 Clock Driver

    Hi Arash -

    The AD9747 CLK+/CLK- interface in figure 29 of the data sheet will work with either SPARTAN3E or ADN4661.

    Thanks,

    Larry

  • RE: BF518F - BF506F SPI communication problem

    Hi,

    I have 10K pull-ups on both ends.

    Moreover I use LVDS: ADN4661 on BF518 side, and ADN4696E on BF506 side.

    Anyway I think that 20Mhz is too quick since I have many other interrupts on BF506.

    Thank you

  • RE: Measuring non-terminated LVDS outputs.

    The ADN4661 outputs are designed for termination with 100 Ohm resistor. D+ or D- can be measured single-ended. The output voltage on either D+ or D- with 100 Ohm termination will typically be about 1V to 1.4V (datasheet typicals - common mode/offset,…

  • RE: any solution for lvds driver from FPGA

    Hello Niulian,

    If I understand correctly, you want to buffer the LVDS outputs from the FPGA in order to drive them across a longer distance?

    What distance do you want to drive across, and at what clock/data speeds? What is at the receiving end?

    The…

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