• ADN2816: Which clock edge does the retiming block of the ADN2816 use to output data?

    Can you tell me which clock edge the retiming block of the ADN2816 uses to
    output
    data? I'm assuming from the datasheet that it uses the rising edge, and that
    the output register has a propogation delay of around 0.74ns?

     

    The…
  • ADN2816 Evaluation Board Documentation

    Could you please send me the documentation the th ADN2816 EVAL Board?

     

    All the ADN281x CDR product shares the same ADN2812 EVB, with special BOM
    assembly instruction.
    Please find the attached ADN2812 EVB application note and the ADN2816…
  • ADN2816 lock time

    Hello guys,

    i got a system picking up data at a more or less constant bit rate of 10Mbit/s. As recovery unit i thought about working with the ADN2816 which offers the desired rate.

    At https://ez.analog.com/message/163320#163320 i found some answers…

  • ADN2816 VRef Voltage & Circuitry.

    I'm trying to interface an LVDS input data stream to the ADN2816.

    Previously I was using capacitors in the line but found they were picking up quite a bit of noise when the data stream was off which was producing unwanted data and clock outputs.

  • ADN2816 Differential Input / Output Voltage ?

    Hi all,

    Our customer is confused about the Input / Output Voltage, Singe-End or Differential.

    "QUANTIZER—DC CHARACTERISTICS
    Peak-to-Peak Differential Input PIN − NIN 0.2(min) 2.0(max) V"

    Here is, I understand this spec is the Differential…

  • Maximum acquisition time of ADN2816

    Hello,

    I have a question about Acquisition Time of ADN2816.
    (normal mode, 10Mb input)

    I can see the "Acquitision Time", it is 40msec, in the table-1 of datasheet.
    But it's a typical value only.
    I'd like to know maximum time of acquisition…

  • RE: Is there IBIS model for ADN2816?

    ADI does not have an IBIS model specifically for the ADN2816, I was told the model for the ADN2813 might suffice

  • What is jitter of ADN2816 output in ps?

    Hello,

    I am wanting to use an ADN2816 clock and data recovery chip as the clock source for an ADC. I need 0.4 ps jitter. The ADN2816 makes great play of using a dual PLL architecture and filter to achieve very low jitter generation and good jitter attenuation…

  • ADN2816: What is the latency between DataIn and DataOut?

    What is the max/min/typical latency between the DataIn and DataOut Signal? Is it depending on any settings?

  •   ADN2816: What is the latency between DataIn and DataOut?

    What is the max/min/typical latency of ADN 2816 between the DataIn and DataOut Signal? Is it depending on any settings?