• RE: Use ADN2816 at the "lock to input data" mode

    Dear Hirose-san,

    Thank you very much for being interested in ADN2816.

    If you configured the ADN2816 in lock to data mode, and disconnected the input signal,

    the ADN2816 would behave as:

    1.     LOL keeps up with intermittent dips. On ADN2816 EVB, the LED…

  • RE: ADN2814 and Hotlink?

    Dear Dave,

    ADN2817 is one any rate CDR, which supports from 10Mbps upto 2.7Gbps, continuous mode (NRZ type, PRBS) data inputs.

    In ADN2817 family, if you are interested in the 167Mbps data link only, you might think about a cost down derivative: ADN2816…

  • RE: ADN2816: What is the latency between DataIn and DataOut?

    Dear Tobi2409,

     

    ADN2816 extracts an embedded clock from a serial input data stream. ADN2816 then uses the recovered clock to sample the ADN2816 input data stream to get the recovered data. During the process, ADN2816 will align recovered clock edges to an…

  • RE: ADN2816 VRef Voltage & Circuitry.

    Dear Brynmor,

    Fig. 20 of ADN2816 datasheet has shown the input stage termination circuitry.

    When you design one DC coupled matching network to link one LVDS output signal to the ADN2816 CML input,

    please satisfy the ADN2816 input common mode levels…

  • RE: Is there IBIS model for ADN2816?

    ADI does not have an IBIS model specifically for the ADN2816, I was told the model for the ADN2813 might suffice

  • ADN2816 Evaluation Board Documentation

    Could you please send me the documentation the th ADN2816 EVAL Board?

     

    All the ADN281x CDR product shares the same ADN2812 EVB, with special BOM
    assembly instruction.
    Please find the attached ADN2812 EVB application note and the ADN2816…
  • ADN2816: Which clock edge does the retiming block of the ADN2816 use to output data?

    Can you tell me which clock edge the retiming block of the ADN2816 uses to
    output
    data? I'm assuming from the datasheet that it uses the rising edge, and that
    the output register has a propogation delay of around 0.74ns?

     

    The…
  • RE:   ADN2816: What is the latency between DataIn and DataOut?

    Dear Tobi2409,

    Have you seen our answer to your previous question: ADN2816: What is the latency between DataIn and DataOut?

    Best Regards,

    Dongfeng

  • RE: ADN2816 lock time

    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
  • Maximum acquisition time of ADN2816

    Hello,

    I have a question about Acquisition Time of ADN2816.
    (normal mode, 10Mb input)

    I can see the "Acquitision Time", it is 40msec, in the table-1 of datasheet.
    But it's a typical value only.
    I'd like to know maximum time of acquisition…