=== ADN2812 CDR ===
The LOL (loss of lock) of ADN2812 is asserted around every 200ms for short period in our system.
The datasheet shows it will return frequency acquisition mode when frequency difference between VCO & incoming data over 1000 ppm. The…
Yes, an external reference clock can help ADN2812 locking to an input data signal after you have set ADN2812 in "Lock to Reference" mode.
To do this, you need to write CTRLA = 1.
In this LTR mode, the ADN2812 locks onto a…
I'm trying to use the ADN2812 to recover an FDDI stream. I’ve been following the reference design (AN-657) as well as AN-746 “Supporting FDDI with the ADN2812." I have the ADN2812 in lock to refclock mode and as long as the FDDI data is sufficiently…
Sorry for my typo, it should be 1.3MHz instead of 1.3kHz.
Did you lock on to an input clock signal or a burst mode PRBS type of modulated data signals?
Both ADN2812 and ADN2913 supports continuous mode, PRBS type, NRZ encoded data signals…
Sorry for the delay. Evaluation board materials have been sent offline.
We recommend the ADN2817 or ADN2818 as "recommended/preferred" instead of ADN2812. ADN2817/8 are newer products.