• RE: ADAU1467 Please let me know the correct timing in the system initialization sequence.

    Hello takumi3952,

    This is shown in the Figure 14 diagram. Basically, until the power has come up and stabilized and the internal level shifters start functioning, then the master clock is allow to reach the PLL. At that point the state of the reset pin…

  • RE: ADAU1452 & MCU connection using Evaluation Board EVAL-ADAU1452

       Hello,
    •    Looking into digital signals generated by the uC output I could realize that the codes did not respect DS spec for the family at all, so I asked customer to manually adapt those. 
    •    Customer had to review the process of "System…
  • Several questions about ADAU1442

    Hello,

    I have a few questions about the ADAU1442:

    1. Do any of the following pins have pullup resistors:

    ADDR0
    ADDR1
    SELFBOOT
    CLKMODE0
    CLKMODE1
    PLL0
    PLL1
    PLL2
    RESET

    When I look at the evaluation board schematics ( www.analog.com/static/imported-files/user_guides…