ADM811 is very low consumption current device.
Can ADM811 use resistive divided input?
I would like to spend 1mA for resistor.
(input voltage is 24V, 100uA enough?)
ADI has more suitable device, I know.
Sorry I could not select other device.
what's the typical input hysteresis and glitch immunity of ADM811?
Thank you for your quickly response!
We find the root cause about this issue(hardware design issue):
The MCU control the ADM811 pin 3(MR), and the ADM811 pin 2(Reset) connct to the ADAU1452 reset pin.
When we pull high…
It may not matter, but I did notice a difference in reset circuits for the two boards. The 1701MINIZ board processes the /RESET from the USBi through the ADM811 (into pin 3 and out pin 2):
Your prototype board directly parallels the ADM811…
As the threshold of the devices are all tested during production test, it’s unlikely an issue with the device.
I would advise the customer to check the grounding of the scope, try measure ADM811’s VCC and RESET by referencing the scope ground…
I would like to add one more thing.
If the ADM811 (or other PSU monitoring system) is triggering a reset when the START_CORE bit is toggled, this indicates a problem in the power delivery system.
A reset generator like the ADM811 toggles reset if the supply…
Hello support people,
I have a question about the output level of ADM811L RESET pin.
In the page-3 of ADM811 datasheet(Rev.G), spesification of minimum level of "high" output is wirtten as "Vcc x 1.5".
According to this, if I use…
I'm having trouble loading the DSP on a EVAL-ADAU1452MINIZ board using our microcontroller. The code is stable and ported from our ADAU1701 target hardware, with the changes required for the ADAU1452.
I'm not confident that I've actually put the…
this is not a solution for the first lock after powering up the ADAU.
There is no problem with the mute function (mute ASRC when lock is lost) if at least one lock is done!
After this you can plug-in/out the toslink without any pop noise.…
This is shown in the Figure 14 diagram. Basically, until the power has come up and stabilized and the internal level shifters start functioning, then the master clock is allow to reach the PLL. At that point the state of the reset pin…