Q 

How can the 1/f noise of the ADM7150/ADM7151 be reduced?

A 

The BYP capacitor value can be increased to reduce the noise below 1 kHz at the
expense of increasing the start-up time of the LDO. Very large values of CBYP
significantly reduce the noise…

Q 

How is the output noise spectral density of an ultra-low noise LDO measured?

A 

Noise measurement equipment such as the Agilent E5505A or E5052B forms the
basis of the noise test fixture.  Since the output voltage noise of the
ADM7150/ADM7151 is…

Presenter: Ian Collins, Staff Applications Engineer

This webcast is an overview of Phase Locked Loop (PLL) Technology and Applications. With over 80 unique PLLs and PLLVCOs, covering frequencies from DC to 18 GHz – ADI has the widest frequency range…

咱们专家在媒体论坛中举办了“集成式软件定义无线电”的技术讲座，介绍了将RF到基带的高速模拟信号链与FPGA数字信号处理相结合，可用于无线通信。话题涉及高速模拟信号链、直接变频无线电架构、高速数据转换器接口以及软件定义无线电中的FPGA数字信号处理。演示使用新一代的模拟器件高速数据转换器、RF和时钟器件以及Xilinx Zynq-7000 SoC。其它话题包括调制器/解调器导致的系统问题，特别是温度和频率变化造成的影响。探讨可以减少这类问题影响的工厂和现场算法，尤其是“一劳永逸”的工厂预制算法…