Hi,The equivalent circuit I designed is shown below.
At the beginning, ADG601 is disconnected and V1 is stable at 3.5V. Then turn on the ADG601 and set VI to 0V. However, because there is a 0.47uF capacitor, the ADG601 may have a large instantaneous…
I'm using ADG601 as shown in the image above. When I provide an high value to SHDN i can correctly see VBatt = +VH. On the other hand, when I provide a low value to SHDN i can not see +VH = 0 V.
Can someone help me in understand…
There are two options that can be an alternative for your simulation:
I was confused with the lines "VCCIO is coming from processor board, VDD is derived on my board from VCCIO, with some delay due to overvoltage protection (about 40 msecs) and soft start, 800 msecs total." and "VDD can't be made…
Here are some answers to your questions: