• ADG324x: Maximum Pass Voltage of the ADG324x Bus Switches

    FAQ: What is the meaning of the “Maximum Pass Voltage” specification listed in the datasheet of the ADG324x bus switches?

    Answer:

    The maximum pass voltage specification on the ADG324x family of bus switches represents the maximum voltage that…

  • ADG324x: Level Translation of ADG324x Bus Switches

    FAQ: How to achieve the level translation in ADG324x switches?

    Answer:

    The signal applied to either the A or B pins of the ADG324x family of bus switches is clamped at the maximum pass voltage level specified in the datasheet. The maximum pass voltage is…

  • Maximum Pass Voltage on the ADG324x bus switches

    Can you please explain the meaning of the "Maximum Pass Voltage" specification listed in the datasheet for the ADG324x bus switches?

    The maximum pass voltage specification on the ADG324x family of bus switches represents the maximum voltage…

  • ADG324x Level Translation: high to low

    The ADG324x family are level translators that is capable of translating voltage levels from high to low only. This statement can be supported by the Truth Tables and is further discussed at the Mixed Voltage Operation, Level Translation Section of the…

  • ADG330x: Level Translator for I2C Applications

    FAQ: Can I use ADG330x for I2C applications?

    Answer:

    The ADG330x is not recommended for I2C applications. The ADG330x architecture shown in the Theory of Operation section of the datasheet uses an internal resistor to ensure the device operates correctly…

  • Level translation with ADG324x bus switches

    How is the level translation achieved with the ADG324x bus switches?

  • Maximum Pass Voltage on the ADG324x bus switches

    Can you please explain the meaning of the "Maximum Pass Voltage" specification listed in the datasheet for the ADG324x bus switches?

  • ADI芯片辨识、型号查找

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  • RE: AD9528 jitter question

    Chapter 9 Hardware Design Techniques F.pdfHi XY,

    let me respond to your questions:

    If we use Buffer Mode, Output Additive Jitter is about 140fs. so total rms jitter for AFE ADC clocks should be roots.quare(100*100+140*140+54*54) = 180.3fs rms. Is my perception…

  • RE: 发帖就送话费啦(限前一百名哦),还有大奖等您拿(获奖名单已公布)

    好资料,在一个论坛下载的,与大家相关的话,可以参考参考