• Level translation with ADG324x bus switches

    How is the level translation achieved with the ADG324x bus switches?

  • Maximum Pass Voltage on the ADG324x bus switches

    Can you please explain the meaning of the "Maximum Pass Voltage" specification listed in the datasheet for the ADG324x bus switches?

  • RE: AD9528 jitter question

    Chapter 9 Hardware Design Techniques F.pdfHi XY,

    let me respond to your questions:

    If we use Buffer Mode, Output Additive Jitter is about 140fs. so total rms jitter for AFE ADC clocks should be roots.quare(100*100+140*140+54*54) = 180.3fs rms. Is my perception…

  • RE: 发帖就送话费啦(限前一百名哦),还有大奖等您拿(获奖名单已公布)


  • ADI技术指南——电路仿真和PCB设计