Hi I am using the ADG1211 is my application board simulation ( downloaded the spice model for AD website). When the switch is off that time I am seeing 500nA of leakage but the data sheet says that it is few pA. Can anybody help me about this.
Unfortunately we do not have a spice model available for the ADG1611 at this time.
What supplies are you using for the ADG1611 model?If the ADG1211 model is simulated with a dual 5V supply the model will not function properly. The ADG1211 is optimized…
Unfortunately ADI does not currently have a SPICE model for the ADG1207. We do provide a model for the ADG1211. This model can be configured to be representative of the ADG1207. The model can be found at the link below.
Yes, you can. The 15V/0V logic input levels actually are recommended to achieve lower Idd consumption. Looking at the Idd vs Logic Level plot of the ADG1211 datasheet, shown below, it is seen that Idd consumption is lowest as logic input level reaches…
And the ADG1211 has the definition of LOWONSWITCH, while I still didn't find the prototype of HIGHONSWITCH subcircuit.
Sorry for the late response.
The track-hold setup time is the time interval before the input voltage is sampled for each tracking cycle in the PWM signals driving the ADG1211 switches. The track-hold hold time the time interval after sampling…
Actually AD5260 and ADG1414 do have a VL input.
Besides, if I read the datasheets correctly, the ESD protection diodes could be forward biased if I supply any voltage higher than the conduction value of such diodes in the wrong order.
Also, even if…
If you have not checked out the AD8034 (FastFET Op Amp) datasheet, then it may help out some more. It has a high-speed peak detector circuit on page 19 which is close to what you may need (see link below).
You may also want to check out the one of our…