The schematics, Gerbers and BOM for the ADF7024 evaluation boards can be found in the ADF7024 design file package which is available from the ADF7024 product page (www.analog.com/adf7024).
The ADF7024 can support payload lengths > 240 bytes. This feature is not discussed in the ADF7024 datasheet or reference manual but is described instead in application note AN-1317: Rolling Data Buffer on the ADF7024.
The application note describes…
The image rejection calibration firmware download is included with the ADF7024 design resource package, which can be found on the ADF7024 product page at www.analog.com/adf7024. For details on the IR calibration algorithm and firmware download, please…
The ADF7024 design resource package can be downloaded from HERE.
There is also is a link from the ADF7024 product page (http://www.analog.com/adf7024) as shown below:
Register and download the ADF7024 design resource package by following this link
The ADF7024 design resource package includes the following:
In the datasheet of ADF7024, it has mentioned that The ADF7024 Reference Manual, UG-698, is included in the ADF7024 design resource package, which is available for download on the ADF7024 product page. But I cannot find this documention on the…
The ADF7024 has two deep sleep modes.
Deep Sleep Mode 2:
Deep sleep mode 2 is the lowest power state of the ADF7024. The typical current consumption in this state is 0.18µA. Deep Sleep Mode 2 is entered by issuing the CMD_HW_RESET command from any radio…
I am having trouble configuring the ADF7024 to enter the deep sleep modes. What procedure should my host processor follow in order to get the ADF7024 to enter and exit the deep sleep modes?
Can I use an external LNA and PA with the ADF7024? If so what support does the ADF7024 provide in terms of control signals for the external LNA and PA?