• Gerber files of ADF4401A

    Could please provide the gerber files of EVAL_ADF4401A which I can not find on the official website?

  • how to design loopfilter of adf4401a


    I would like to ask you experts how to design the peripheral circuit parameters of the LT6200 for the loop filter of the ADF4401A?


  • how to simulate phase noise of adf4401a with different LO

    I bought several pieces of adf4401a some time ago. Now I tested it with its EVAL_Board for some time. I want to simulate the phase noise of adf4401a with LO in different levels of phase noise  when it is locked. Could I achieve it through ADIsimPLL or how…

  • ADF4401A ‘integrated doubler for 8 & 8.8GHz’

    Hi Support

    On the Analog Devices product page for the ADF4401 a video is available presented by Kazim Peker entitled ‘Perfection of Translation Loop: Eliminating Spurious Signals’.  On slide 17 an ‘integrated doubler for 8 & 8.8GHz’ is mentioned…

  • Translation loop or traditional PLL using a N divider, which to choose?

    ADF4401a uses a mixer to down convert the VCO output frequency for a PFD while traditional PLLs use a N divider to divide the VCO output frequency to a relative low frequency for PFD. So which solution is better? What is the difference in the final output…

  • RE: EV-ADF4401ASD2Z Evaluation Board's output is off frequency in Translation Loop mode

    I'm glad you were able to get this working.

    HMC3716 will accept a 10 MHz square wave signal, but due to filtering on the ADF4401A's IF path, the IFoutput will be severely attenuated at 10 MHz. The external reference and IF signals must match in frequency…

  • RE: Can you elaborate on lowest phase noise solution for instrumentation?

    Our lowest phase noise production released PLL+VCO is the ADF4401A which provided DRO type phase noise performance but implemented with a PLL+VCO translation loop architecture by using the SMA100B for the Offset LO. The ADF4401A offers <10fs RMS wideband…

  • RE: ADF4155 frac-N PN Floor PLLsim vs Datasheet?

    Hi Mike,

    I can't send any modified PLL models as these will only work on our custom in-house/debug version of ADIsimPLL for internal use only - the PLL models are fixed otherwise.

    We weren't able to get this fix into the ADisimPLL v5.4 release, but…

  • RE: If I wished to deisgn the best Phase Noise solution what is the device that delivers unparallel perofrmance?

    Great question..it really depends on your application but if we had to choose one device to single out on the vector of performance above all else then it’s the ADF4401A Translation Loop IC. It’s a novel architecture that is used in INST applications…