• ADF4372 SCLK Falling Edge to Data Out (Muxout) Valid Delay (Taccess)


    The ADF4372 datasheet (https://www.analog.com/media/en/technical-documentation/data-sheets/adf4372.pdf) specifies a SCLK Falling Edge to SDIO Valid Propagation Delay, Taccess, of 10ns. This number is listed in the "Min' column and there are no other…

  • How to config ADF4372 PLL in divider feedback path?

    I have a design , the ref clock and PFD is 12.5Mhz input,  i need PLL output is 100Mhz, and the output 100Mhz

    must has the same phase relationship with the ref clock(12.5Mhz) every time when power up,  so i select ADF4372

    and use vco divider feedback paht…

  • ADF4372 differential-ended output to signal-ended output

    Dear Team,

    We are planning to use ADF4372 chip in single ended output mode,We cannot find the hardware connection for single ended output in datasheet.Kindly provide hardware circuit connection for single ended output.



  • ADF4372- Clock Generation in Fractional Mode

    Hello ADI Team,

    I am using ADF4372 PLL for generating Output Clock with frequency 12451.84 MHz in Doubler path (RF16).

    Reference input frequency is 409.6 MHz

    PFD Frequency is 102.4MHz

    Hence N divider value is 60.8.

    What will be value for INT, FRAC1, MOD2…

  • Phase difference between RF8P, RF8N VS RFAUX8P, RFAUX8N of ADF4372

    Dear team,

    We are planning to use ADF4372 in our design.Kindly share the phase difference details between RF8P, RF8N VS RFAUX8P, RFAUX8N.



  • ADF4371 vs. ADF4372 output power

    I have measured the output power from the RF8 port on an ADF4371 evaluation board.  I'm planning on using an ADF4372 on a new design.  In terms of output power, can I assume the performance on the RF8 port is the same between these two parts?

  • About ADF4372 output spectrum

    Hi all

    As shown in the problem, when ADF4372 tests the output signal, it is found that the bottom noise of the output signal is raised in decimal mode. It shows that there are moving spurts around the proximal end of the spectrum line, as shown in the figure below:

    The integer mode is normal, as shown 

  • ADF4372锁相环输出幅度问题?



  • RE: the output amplitude of adf4372

    Marking as answered due to lack of activity

  • Max Power Consumption for ADF4371 & ADF4372


    What is the max power consumption for ADF4371 & ADF4372?