• ADF4372 / ADF4371 initialization

    Hi ADI

    I'm want to setup my ADF4372, however some of the the datasheet descriptions of the various registers are a bit obtuse and it's not obvious how I should set them up. I have an ADF4371 eval board which I can set up to my wanted frequency using your…

  • ADF4372 LEV_SEL not responding

    Hi ADI

    We're using your ADF4372 and can't seem to get the LEV_SEL bit to respond. The SDIO and MUXOUT pins only seem to give out 1.5V for a logic high not matter what the setting of the LEV_SEL bit?  Please can you help? We seem to be able to talk…

  • ADF4372 3.3V Operation

    I have two questions:

    1. What voltage is VCC_REG_OUT?

    2. What changes to the circuit need to be made to change from VCC_VCO=5V to VCC_VCO=3.3V operation?



  • Can the ADF4372 tolerate a sweeping reference clock?

    Hello, I am using the ADF4372 and intended to having a sweeping reference clock which would get 1000x multiplied in the chip. So far, I can successfully pipe out the low ends and upper ends of the sweep, but only if I rewrite the registers after sweeping…

  • ADF4372 & rpi-5.10y analog devices kernel build

    Hello everyone

    I am trying to rebuild the kernel for ADF4372 driver : below


    Now it don't work well.


    Linux raspberrypi 5.10.631235984-v7 #4 SMP Sat Jul 16 17:41:54 JST 2022…

  • ADF4372 SCLK Falling Edge to Data Out (Muxout) Valid Delay (Taccess)


    The ADF4372 datasheet (https://www.analog.com/media/en/technical-documentation/data-sheets/adf4372.pdf) specifies a SCLK Falling Edge to SDIO Valid Propagation Delay, Taccess, of 10ns. This number is listed in the "Min' column and there are no other…

  • How to config ADF4372 PLL in divider feedback path?

    I have a design , the ref clock and PFD is 12.5Mhz input,  i need PLL output is 100Mhz, and the output 100Mhz

    must has the same phase relationship with the ref clock(12.5Mhz) every time when power up,  so i select ADF4372

    and use vco divider feedback paht…

  • ADF4372 differential-ended output to signal-ended output

    Dear Team,

    We are planning to use ADF4372 chip in single ended output mode,We cannot find the hardware connection for single ended output in datasheet.Kindly provide hardware circuit connection for single ended output.



  • ADF4372- Clock Generation in Fractional Mode

    Hello ADI Team,

    I am using ADF4372 PLL for generating Output Clock with frequency 12451.84 MHz in Doubler path (RF16).

    Reference input frequency is 409.6 MHz

    PFD Frequency is 102.4MHz

    Hence N divider value is 60.8.

    What will be value for INT, FRAC1, MOD2…

  • Phase difference between RF8P, RF8N VS RFAUX8P, RFAUX8N of ADF4372

    Dear team,

    We are planning to use ADF4372 in our design.Kindly share the phase difference details between RF8P, RF8N VS RFAUX8P, RFAUX8N.