• ADF4372 3.3V Operation

    I have two questions:

    1. What voltage is VCC_REG_OUT?

    2. What changes to the circuit need to be made to change from VCC_VCO=5V to VCC_VCO=3.3V operation?

    Thanks,

    Michael

  • How to config ADF4372 PLL in divider feedback path?

    I have a design , the ref clock and PFD is 12.5Mhz input,  i need PLL output is 100Mhz, and the output 100Mhz

    must has the same phase relationship with the ref clock(12.5Mhz) every time when power up,  so i select ADF4372

    and use vco divider feedback paht…

  • ADF4372- Clock Generation in Fractional Mode

    Hello ADI Team,

    I am using ADF4372 PLL for generating Output Clock with frequency 12451.84 MHz in Doubler path (RF16).

    Reference input frequency is 409.6 MHz

    PFD Frequency is 102.4MHz

    Hence N divider value is 60.8.

    What will be value for INT, FRAC1, MOD2…

  • ADF4371 vs. ADF4372 output power

    I have measured the output power from the RF8 port on an ADF4371 evaluation board.  I'm planning on using an ADF4372 on a new design.  In terms of output power, can I assume the performance on the RF8 port is the same between these two parts?

  • About ADF4372 output spectrum

    Hi all

    As shown in the problem, when ADF4372 tests the output signal, it is found that the bottom noise of the output signal is raised in decimal mode. It shows that there are moving spurts around the proximal end of the spectrum line, as shown in the figure below:

    The integer mode is normal, as shown 

  • ADF4372锁相环输出幅度问题?

    adf4372

    本人在使用ADF4372芯片时,运用RF16输出口,锁相环正常锁定,但是输出幅度只有-28dbm,这是为什么,请求解答谢谢。没有在VDDX1加7.4nH电感。

  • RE: the output amplitude of adf4372

    Marking as answered due to lack of activity

  • Max Power Consumption for ADF4371 & ADF4372

    Hi, 

    What is the max power consumption for ADF4371 & ADF4372?

    Thanks.

  • ADF4372- AMI Model Request

    Hi ADI Team,

    I am planning to use ADF4372 in my design.

    I need the AMI Model for Signal integrity Analysis.

    Please share that model as soon as possible.

    With Regards,
    Sakthi

  • ADF4372失锁

    本人使用ADF4372生成时钟时,发现pll始终无法锁定,测试muxout后发现r分频输出50MHz时钟时,N分频输出约49.2MHz,请问大神们这是否正常?如何解决。本人电路如下  图所示