I am looking for the drift of the VCO  in the ADF4360-7.  I understand that the output of the VCO is ± 3 dB Typ over the full temperature range is discussed here:

https://ez.analog.com/message/86637#86637

I am looking for how the frequency changes with…

Hi,

Is it possible to have a single-ended RF output from ADF4360-7.
If it is possible, is it just enough to connect unused RF output pin to ground via a 50 ohm resistor or should I use a balun ?

Thanks in advance.

The ADL5350 needs about 4dBm LO drive. In my case the LO is around 1700 MHz. Do I need a balun and a LO buffer to use the ADF4360-7 as the LO source? Or perhaps some smart trick allows me to connect it differently as LO harmonics is not important as the…

您好，我想咨询贵公司的产品ADF4360-7的DesignKit问题，请问在哪里可以下载到？我在用ADS软件对ADF4360-7进行仿真，需要导入ADF4360-7的DesignKit，但是没有找到相应的下载地址，方便的话把地址发给我。谢谢。

Hi All,

Today, one customer asked me about behavior of ADF4360-7 power down mode.

Then, I have following questions about it.

When get CE to low and power down the device,

1. what should be expected as the state of MUXOUT(digital lock detect mode…

Datasheet says that "ADF4360-7 can be used at many different frequencies simply by choosing the external inductors to give the correct output frequency." Graph on Fig.24 shows that if we need center frequency to be at 400MHz, value of both inductors…

我现在对ADF4360-7输入10MHz的信号，让其产生1.25GHz信号，并对产生的1.25GHz信号进行延时方案如下：

利用FPGA对输入的10MHz信号控制延时，从而达到对1.25G输出信号的延时

但是我看了一个analog公司一个关于PLL的英文文档如下图，它是ADF4360-7中的一部分，U3的输出需要经过一个DELAY延时电路，如果采用第二种方案会不会影响延时控制，使得信号延时失去意义，由于个人水平有限不确定U3 ，DELAY,IN,+IN-会不会对延时产生影响，我不知道控制10M输入信号…

我的电路采用的是ADF4360-7的芯片手册中的原理图（如下图），想要输出一个1GHz的时钟信号，输入是10MHz。程序是FPGA写入，写入后用示波器测MUXOUT的输出，串行数据和R分频输出都是有波形，且正确，但是N分频没有输出，想请问大家这有可能是什么原因？电感我试了2.2nH和3.3nH的绕线电感，都不行

Hi,I want to know the difference about the ADF4360-7's package in the CP-24-14 and CP-24-2.Can I use the  CP-24-14 and CP-24-2 in the same  PCB  PACKAGE?

THANKS!EmmaChen