Hi all,

I am trying to use the adf4350 Linux kernel driver on a my Beaglebone embedded board.

The driver is compiled correctly (also because it's already included in the kernel source), but nothing is working as reported here in the Driver Test…

Hello,

I programmed the registers as shown in 1000-registers.JPG and I got 1000-spe-ana.jpg on the spectume analyzer but when I changed the frequency to 850-registers.JPG,  then I got  850-spe-ana.JPG.... could you explain why? Thanks! Gio

Hii there,  I Intend to control the Eval-ADF43500EB1Z through a network connection(using RJ45).  Is it possible to do so?

How about the graphical PC control source code (Visual Basic or Visual C++ based ) that comes with the ADF4350 Evaluation board.…

Recently I tested my ADF4350 card

1.The fundamental spectrum(2.2 -4.4)GHz is fairly pure

2.When I use divider in PLL to  generate frequencies less than 2.2GHz (say1.2GHz)I can see

lot of spurious In addition to Harmonics.Those spurious are with an…

Hi to all, I'm playing with my own software for ADF4350 and I'd like to know if after first initialization of registers R5, R4, R3, R2, R1 and R0 to generate new frequency, for example, it's correct to update only R4 for new RFDIV,  R1 and…

Are the timing characteristics for the ADF4350 three wire interface shown on p5 of the data sheet correct ? We have not been able to get this to work as described.

Specifically, a rsing clock edge in the middle of the data bit does not work (data setup…

I have a customer
that is doing development of control code for the ADF4350, for a proprietary
project for his client. He was able to work with the ADF4350 eval board using
the supplied AD control software. They are working to develop their own
software to…

We are experiencing a weird thing that the ADF4350 LD pin is always HIGH, or the locked LED is ON even if the output frequency is wrong. 

#1

For example, we have 10MHz REF IN and set ADF4350 to have 1600MHz output.

However the output is 2200MHz instead and…

Ths is comment on recent posting of an App Note

Achieving phase coherence between multiple Fractional-N PLLs

ADF4350 Phase Resync and Phase Programmability

Please post the two references cited as hyperlinks - 'here' - I could not click into them…