• FAQ: Extending the VCO tuning range of the ADF4193 ultra fast settling PLL


    How do I get extended VCO tuning range using the ADF4193?



    Fastlock in PLLs is a technique whereby the PLL…

  • RE: Extending Tuning Voltage of ADF4193

    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
  • ADF4193 unlock

    Hi,recently our customer designing ADF4193 refer to Evaluation Board sch.However the frequency always unlock.

    Can you help support relative configure reference code? Thanks.

  • ADF4193锁定标准的问题,帮忙看一下,多谢







  • ADF4193宽带频率输出快跳锁定问题


  • ADF4193, ADF4196 evaluation boards software

    The latest ADF4193 and ADF4196 software (v6) is attached.

    Installation process:

    1. Disconnect any evaluation board

    2. Download and run the attached installer

    3. Click Next/Continue/Finish when asked

    4. Connect your evaluation board

    5. Windows will…

  • ADF4193 manual bandwidth register setting

    In the ADF4193 eval board software, there is a setting to lock the PLL into wide bandwidth mode, which was useful for us in debugging some stability issues with an external op-amp. Now that we have the board back, I don't see the register setting that…

  • ADF4193 register map query

    I have a quick query regarding the ADF4193 register map. Unlike the ADF4351, the 4193 has registers of a differing number of bits (p.14 of D/S). However, I presume that as you write the control bits last due to the serial programming being MSB first that…

  • ADF4193 Does Sim PLL predict integer boundary spurs

    Doing a  design with ADF4193 Does SimPLL account for integer boundary spurs?  Fref is 25MHz, Mod=250,  loop BW is 80KHz, operating from 2.45 GHz to 2,68GHz with a channel spacing of 100KHz.  I have done calcutations on a spread sheet for the integer boundary…

  • RE: Lock time of the ADF4252

    Lock time depends on PLL loop bandwidth. Wide loop bandwidths lock quickly. Narrow ones slowly.

    Download ADIsimPLL to get an estimate of performance.

    For fast locking applications the ADF4193 is the fastest part we have.