• FAQ: Extending the VCO tuning range of the ADF4193 ultra fast settling PLL

    Q.

    How do I get extended VCO tuning range using the ADF4193?

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    A.

    Fastlock in PLLs is a technique whereby the PLL…

  • RE: Extending Tuning Voltage of ADF4193

    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
    …

  • ADF4193 unlock

    Hi,recently our customer designing ADF4193 refer to Evaluation Board sch.However the frequency always unlock.

    Can you help support relative configure reference code? Thanks.

  • ADF4193锁定标准的问题，帮忙看一下，多谢

    你好，请教个关于本振的问题：

    ADF4193的锁定：从手册上看，当前向分频之后的频率和VCO输出频率分频之后两个频率差在一定范围之内，内部逻辑

    检测到连续几个脉冲之内在范围内，就判定为锁定，从手册上看是3ns，是不是可以这样理解：

    如果输入频率：10MHz，输出频率：400MHz，鉴相频率为10MHz

    这样鉴相周期就是：1/10MHz：100ns，如果差异在3ns，那么假定参考是精确的，那么输出经分频之后的周期就为97ns或者是103ns，这样考虑N分频输出频率就为

    412.37MHz或者388…

  • ADF4193宽带频率输出快跳锁定问题

    利用ADF4193作为鉴相器，输出频率带宽1500MHz(如1500--3000MHz输出，步进1MHZ)频率转换时间最快可达多少us?环路滤波器需加运算放大器，电路如何实现及如何仿真环路？

  • ADF4193, ADF4196 evaluation boards software

    The latest ADF4193 and ADF4196 software (v6) is attached.

    Installation process:

    1. Disconnect any evaluation board

    2. Download and run the attached installer

    3. Click Next/Continue/Finish when asked

    4. Connect your evaluation board

    5. Windows will…

    • ADI_ADF4193-6_Setup_v6_3.zip

  • ADF4193 manual bandwidth register setting

    In the ADF4193 eval board software, there is a setting to lock the PLL into wide bandwidth mode, which was useful for us in debugging some stability issues with an external op-amp. Now that we have the board back, I don't see the register setting that…

  • ADF4193 register map query

    I have a quick query regarding the ADF4193 register map. Unlike the ADF4351, the 4193 has registers of a differing number of bits (p.14 of D/S). However, I presume that as you write the control bits last due to the serial programming being MSB first that…

  • ADF4193 Does Sim PLL predict integer boundary spurs

    Doing a  design with ADF4193 Does SimPLL account for integer boundary spurs?  Fref is 25MHz, Mod=250,  loop BW is 80KHz, operating from 2.45 GHz to 2,68GHz with a channel spacing of 100KHz.  I have done calcutations on a spread sheet for the integer boundary…

  • RE: Lock time of the ADF4252

    Lock time depends on PLL loop bandwidth. Wide loop bandwidths lock quickly. Narrow ones slowly.

    Download ADIsimPLL to get an estimate of performance.

    For fast locking applications the ADF4193 is the fastest part we have.