• ADF4157 relation between Icp and Loop filter design


    I am using EV-ADF411XSD1Z eval kit with ADF4157.

    According to the datasheet the value in DB[27:24] set the charge pump current setting. This should be set to the charge pump current that the loop filter is designed with.

    Can you please help on the…

  • the PLL circuit using ADF4157 is always unclocked

    I designed a PLL circuit using ADF4157. The VCO module of the PLL is a board VCO I designed myself. The output frequency of the VCO is about 1.250GHz. Kv is 6MHz/V ,and it can work properly. I use 51MCU(STC89LE52RC) to configure of the register of ADF4157…

  • ADF4157用于高分辨率应用


  • how to improve the IBS in fractional PLL ADF4157?

        I use ADF4157 to design a PLL with frequency range 1GHz~2GHz ,freq step 1kHz,loop filter band width 50kHz.during loop band,the IBS tested is about  -48dBc,How can I improve the IBS in loop band?

  • RE: Generate accurate 115.1859375MHz frequency

    You should also look at the ADF4157. The ADF4157 has a 25 bit modulus which, for a 10 MHz PFD frequency, give you an output resolution of 0.298 Hz. This should be enough to get your exact frequency.

    The minimum RF input of the ADF4157 is 500 MHz. However…

  • RE: ADF4350 minimum channel spacing and freq error

    I don't think the ADF4350 is suitable on it's own for this application.

    A channel spacing of 20 Hz requires 80 kHz PFD frequency which is possible but will degrade in-band phase noise (because of the high N value). We offer an ADF4157 stand alone…

  • RE: ADF4150HV - 2 channels have the same hex values

    You can lower your PFD frequency using the R counter. However, this will degrade your phase noise performance. You can simulate the system, and the phase noise, in ADIsimPLL. Free download: www.analog.com/adisimpll

    The ADF4157 Vp is up to 5.5 V. You…

  • RE: EVAL-ADF411xEBZ1 problem

    Is there a loop filter on your board? Are R1, R2, C1, C2 and C3 populated?

    ADF4153, ADF4154, ADF4156, ADF4157 software can be downloaded here:


  • RE: Question about the ADF4351 device.

    My mistake - I didn't see the 1 Hz channel spacing requirement.

    1 Hz channel spacing is very narrow. The channel spacing is generated by PFD frequency/MOD. The maximum MOD on the ADF4351 is 4095 so your maximum PFD frequency will be around 4 kHz…

  • RE: Strange traveling spur problem seen in ADF4113HV

    Here is a brief video of the spectrum of the synthesizer.  I have seen this before in the ADF4157 fractional N PLL, but I find this very strange behavior in an integer-N PLL.   The reference clock seems clean when observed on the spectrum analyzer (i.e.…