I just downloaded the REV A specification for the ADF4157. I see it has a fast lock mode along with the CSR. It does not appear that ADIsimPLL 3.1 supports the ADF4157 in fast lock mode. Is this true or am I missing something here?
Dear,
I used ADF4157(fractional mode) with OP27 to control the VCO(DCMO190410)
I found that some noise were running on the Fout(desired frequency) its like modulated signal.
my design rule as below
loop bandwidth=40KHz
phase margin =45 degree
filter…
Dear Sir,
I had a question for ADF4157 and please see the attachment.
While I had write all registers and why the phase seems shift the 90 degree??
Thank you.
Noted that the ADF4157 datasheet is specified only to 6GHz. I would like to use this chip with an external 6.3GHz VCO for a room temperature application. Is there any reason this chip will not fucntion in this application? If so, what are they besides…
Hi there,
Good day!
Is there any user guide of ADF4157 EVB available, which is similar to ADF4158’s UG-123?
Moreover, I also wonder whether ADF4157 EVB is using USB interface to PC.
Thanks in advance for your great help!
BR,
Alex
Hi,
From what I can see, the channel spacing can’t be set at desired increments as the denominator is fixed at 33554432. As stated in the data sheet, the resolution is REF/33554432. So, for 62.5KHz channel spacing I guess I have to work out the codes…
I have a ADF4157 with the configuration shown in this screenshot
when I probe the output signal with the spectrum analyzer I can see a clean spectrum, however the Digital Lock Detect is not asserted at the MAXOUT pin. Any idea what config has been…
Hi, there
I have a question on ADF4157 when sweeping frequency. PLL output frequency band is 5.8GHz ~ 6GHz. Sweeping step is 1MHz or 2MHz with fPFD of 10MHz. When measuring the output of sweeping, there are glitches available at every 10MHz when sweeping…
The latest ADF4153, ADF4153A, ADF4154, ADF4156 and ADF4157 evaluation board software is attached.
Windows XP, Vista, 7 compatible.
I am using the ADF4157 fractional N PLL chip and have observed some strange behavior in the digital lock detect.
First, the operating conditions:
1) Frf = 1.68GHz
2) Fref = 12MHz
3) Fcp = 12 MHz (phase detector freq is the same as the reference clock…