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TAGS LIST: Clock and Timing

karinasmith

LTC6953

LTC6955

LTC6957-1

HMC6832

HMC7043

LTC6950

LTC6954

HMC987

AD9576

AD9508

HMC1035

HMC988

HMC1033

HMC1034

HMC1032

HMC1031

ADN4670

ADCLK944

ADCLK950

ADCLK948

ADCLK846

ADCLK954

ADCLK946

ADCLK854

AD…

over 3 years ago
Clock and Timing
Documents

RE: phase locked loop IC

ADIApproved

All our PLLs compare the VCO feedback signal, divided by N, with the reference signal, divided by R.

If the R signal pulse hits the PFD (Phase Frequency Detector) before the N signal pulse, then the Charge Pump will pump up to increase the RF frequency…
- over 7 years ago
- RF and Microwave
- Q&A
RE: ADF4158 - Is it possible to modulate a VCO from 11.5 - 12.5GHz

ADIApproved

You could use the ADF4158 and the ADF5001 divide-by-4 prescaler for your circuit. See this solution for reference: http://www.analog.com/en/circuits-from-the-lab/CN0174/vc.html

Just replace the ADF4156 with the ADF4158 and replace the VCO with one for…
- over 10 years ago
- RF and Microwave
- Q&A
Comment on ADF4157用于高分辨率应用

adiadmin

ADF4157适合此应用。例如，如果你使用10 MHz的PFD频率(Fpfd)，那么最小通道间隔为：10 MHz ÷ (2^25) = 0.29802 Hz。如果是1 kHz的通道间隔，那么FRAC间隔 = 3355。输出频率 = (INT + FRAC/MOD) * Fpfd。因此，对于300 MHz：INT = 30；FRAC = 0。(30 + 0/(2 ^ 25)) * 10 = 300 MHz。现在，对于300.001 MHz： INT = 30; FRAC = 3355. (30…
- over 9 years ago
- Power 中文专区
- 文档

ADI中文技术论坛：专家解答热帖（2013年10月汇总）

JValeriani

ADI中文技术论坛：专家解答热帖（2013年10月汇总） by adiadmin

LDF文件有关input section的问题
http://ezchina.analog.com/message/9795#9795

BF537-EZ-KIT Lite 开发板的仿真问题
http://ezchina.analog.com/message/9801#9801

运放的轨到轨是什么意思？
http://ezchina.analog.com/message/9826#982…

over 3 years ago
知识库
文档

RE: a Vco for my ADF7021-V

ADIApproved

Hi Cedric,

Yes it is possible to use an active loop filter. An example of one is attached.

You can simulate this in ADIsimPLL by selecting the ADF4156 to mimic the ADF7021-V.

With this you must ensure that he charge pump currents match.

The gain is…
- ACTIVELOOPFILTEREXAMPLE.bmp
- View
- Hide
- over 11 years ago
- RF and Microwave
- Q&A
Serial Data Output of PLL devices

ADIApproved

ADI PLLs are typically programmed using a three-wire serial interface, where the serial programming data is clocked into an internal shift register and is then latched onto the internal data bus on a rising edge of latch enable (see SPI Programming section…
- AN-xSerialDataOutput.pdf
- over 9 years ago
- RF and Microwave
- Discussions
RE: ADI 可用于 5G技术的资料大起底！

ternence

Part 3：参考电路

1）用于3G、4G和LTE通信系统的宽带低失真发射器

该电路是一个宽带低失真RF发射器，集成双通道高速TxDAC+数模转换器(DAC)、宽带I/Q调制器和输出驱动器放大器。器件匹配良好，且DAC与调制器、调制器与驱动器放大器之间直接接口，可为包括3G、4G和LTE在内的很多RF通信应用提供紧凑型解决方案。

http://www.analog.com/cn/design-center/reference-designs/hardware-reference-design…
- over 4 years ago
- 中文资源库
- 讨论

ADI中文技术论坛：专家解答热帖（2013年10月汇总）

adiadmin

LDF文件有关input section的问题
http://ezchina.analog.com/message/9795#9795

BF537-EZ-KIT Lite 开发板的仿真问题
http://ezchina.analog.com/message/9801#9801

运放的轨到轨是什么意思？
http://ezchina.analog.com/message/9826#9826

…

over 8 years ago
知识库
讨论

RE: External Trigger for AD9625 with HSC-ADC-EVALEZ

ettien_mc2

Hi Irem i do have the same problem like you. I use the AD9656 with the HSC-ADC-EVALEZ, I want to trigger the the capture with a ramp statut generated by the the ADF4156 synthetiser.

Here is attached some quick description of the trigger step. It didn…
- over 3 years ago
- High-Speed ADCs
- Q&A