• RE: SD-Modulator Reset

    Unfortunately, no.

    However, if you are using the ADF4156, you can use the Phase Resync feature to synchronize phases. If you are using the ADF4159, you can use the phase programmability feature to change one phase relative to another.

  • RE: SimPLL ADF4158 Function Issue

    It seems that the CSR feature was omitted from the ADF4158 library model. We will add it next time we do an update. As a workaround you should be able to do an equivalent design with an ADF4156 and check the effectiveness of the CSR feature on lock times…

  • RE: Digital lock detect problem on ADF4157.

    Unfortunately, digital lock detect becomes unreliable when using negative bleed current. More details about negative bleed here: http://www.analog.com/static/imported-files/application_notes/AN-1154.pdf

    Why are you using the ADF4157? Is your fractional…

  • RE: EVAL-ADF411xEBZ1 problem

    Is there a loop filter on your board? Are R1, R2, C1, C2 and C3 populated?

    ADF4153, ADF4154, ADF4156, ADF4157 software can be downloaded here:

    http://ez.analog.com/message/38414#38414

  • RE: ADF4351 Typical Maximum Frequency

    The part can operate up to about 4.5 GHz but normal operation beyond 4.4 GHz cannot be guaranteed and performance may become unpredictable.

    What are your system requirements (channel spacing, reference frequency)? The ADF4156 PLL is similar to the ADF4351…

  • RE: ADF4158 sweep and eval board

    1) For VCO tuning ranges greater than a PLL's Vp voltage requires using an active loop filter. The active loop filter has an op amp which gains the tuning voltage up to the required range. This reference design shows you how the circuit works: http…

  • 关于参考电路CN0174

    Dear:

       最近看到参考电路CN0174《使用有源环路滤波器和RF预分频器的低噪声12 GHz微波小数N分频锁相环》,看到其12 GHz PLL 的测量性能与仿真相位噪声性能对比图。我不知道,在设定的参数下,是如何仿真得到在12GHz输出时相位噪声达到-130dBc/Hz@1kHz。如果相噪按6dB倍频恶化,从100MHz参考输入,鉴相频率25MHz,算上ADF5001的预分频系数,12GHz频率分频到鉴相频率,共有480次分频。这种情况下,相位噪声是如何实现或如何计算仿真到图示中的性能的?…

  • RE: PLL Selection

    Hi Kevin,

    To achieve the 1kHz resolution across the full-band I think he will have to use a fractional-N PLL, like the ADF4156. The problem would

    be sourcing a VCO that can cover his range of 5MHz to 100MHz.

    One circuit suggestion would be to use a…

  • ADF7021-V loop filter design

    Hi,

    I am trying to develop a design using the ADF7021-V with an external VCO. I am looking to find the values for an active loop filter with gain to allow me to use a Crystek VCO, however in a previous post it is recomended to use the ADIsimPLL tool…

  • TAGS LIST: Clock and Timing

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