• Clocking the AD9789: ADF4150 + ADCLK914 or ADF4150 alone?

    Hello,

    A couple of years ago we designed a PCB prototype using the DAC AD9789 clocked by a 2340 MHz VCO from RFMD squared up by the ADCLK914. The VCO was locked to an external 10 MHz reference using the PLL ADF4153. The designed met the specs by far…

  • ADF4150

    How to set output divider of ADF4150 to disable?

  • ADF4150 VCO choose

    Hello

             Customer would like to choose 983.04MHz VCO then hope to get 122.88MHz on RFOUT. How to confirm PLL is locked while no any SPI configuration? Are correct for below pin status while PLL locked? 

    LD Pin(External Pull High): High

    MUXOUT: High

    CPOUT…

  • ADF4150 question

    Hello

                Customer use reference clock is 40MHz and output 122.88MHz. The phase noise specification as below. If use ADF4150 for simulation, below are customer questions, 

    1. Phase detector output is present on abnormal condition when we set the PDF…

  • ADF4150 output 122.88MHz

    Hello

              If customer would like to fractional PLL to support precise 122.88MHz output frequency that external reference frequency input is 10MHz.

              Does ADF4150 that fractional PLL meet customer requirement ? We do PLL simulation that ADF4002 also…

  • ADF4150 Noise characteristics test conditions

    Hello

    I have a question about ADF4150.


    I would like to know about the RF output buffers: -75dBc Typ of Spurious Signals Due to PFD Frequency in the data sheet P4.

    Question

    Please tell me about the conditions when this data was acquired.

    The information…

  • ADF4150 charge pump current!

    We are using ADF4150BCPZ (part number adf4150 #1121 31984)

    We want to control charge pump current value. In order to do this we write value "10007F82" to the Register2. Then we update the chip with the Register0 changing. We detect the current changing…

  • ADF4150 phase resync

    I have a customer using the ADF4150 in a project and they want to utilize the phase resync function. The PLL is setup for fractional N, but at times the modulus is set to 0 when they hit a frequency that is a exact multiple of the reference. Is there…

  • ADF4150 programming library

    I would like to know if it's possible to program the registers of the ADF4150HV Evaluation Board using C/C++ instead of the provided software. We are integrating this kind of boards in our control system and since the values must be rewritten every…

  • ADF4150 low frequency operation

    Hi, 

    I see the ADF4150HV is spec'd for low frequency operation on the ref and RF in with a minimum slew rate.  The ADF4150 only mentions the ref, not the RF.  Has this variant been tested below 500MHz?

    Thanks

    Daniel