• ADF4118 Reference Input Sensitivity

    Hi all,

    In the datasheet specifications, Reference Input Sensitivity at ADF4118 & other ADF Integer-N is following.

    "Reference Input Sensitivity 0.4 to AVDD  V p-p min to max AVDD = 3.3 V, biased at AVDD/2"

    Other test condition is AVDD = 3…

  • ADF4118 VCO direct FM modulation circuits

    Hi all,

    Our customers evaluate the ADF4118 for FM modulation wireless microphone with VCO direct modulation.
    When the power supply on/off is evaluated, the PLL lock time may vary.
    At this time, confirming each voltage of Charge Pump Power Supply Voltage…

  • ADF4118 not powered up

    I have fabricated the PLL according to the datasheet, I have also checked the design accordingly for any open or short circuit errors. As soon as I switched on the power supply and apply it to Vdd the chip is not drawing any current as if it is open-circuited…

  • RE: ADF4118无法锁定

    This question has been closed by the EZ team and is assumed answered.
  • RE: ADF4118 phase alignment across frequency changes

    I believe it will transition smoothly providing that no cycle slips occur.

    These can be observed in simulation using ADisimPLL, and generally occur if the loop bandwidth is very small (compared to the PFD frequency).

  • RE: Query on ADF4118

    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
  • RE: A strange behaviour in ADF4118 lock times

    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
  • ADF4118 - 1MHz reference input

    good morning everyone, i'm having trouble working with a reference input of 1MHz with the ADF4118.

    i'm using an evaluation board (EVAL-ADF411XEBZ1) and a custom board i designed and i'm getting the same behavior (i suspect that i'm making a mistake…

  • RE: ADF4118 S-Parameter Data for RF Input of PLL Circuit

    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
  • Driving ECL input from ADF4118

    I need to generate a clock of a precise frequency to be used as a time base. The time base frequency will be one of 1.6 GHz, 2 GHz or 2.5 GHz, preferably 2.5 GHz. For 1.6 GHz the ADF4360-4 which has an internal VCO seems like a reasonable solution, but…